Preparation method of trench gate applied to trench type MOS device

Abstract

The invention discloses a preparation method for a trench gate of a trench type MOS device. The preparation method comprises the following steps: (1), forming a trench at a silicon wafer needing trench gate manufacturing by using photoetching and etching methods; (2), carrying out first gate oxide layer growth; (3), carrying out coating and baking of a photoresist; (4), forming a photoresist graph at a top corner of the trench; (5), removing the first gate oxide layer except the one at the top corner of the trench by using a wet etching method, keeping the first gate oxide layer at the top corner of the trench, and then removing the photoresist graph; (6), carrying out second gate oxide layer growth; (7), carrying out polycrystalline silicon filling; and (8), forming a needed trench gate structure formed by the polycrystalline silicon and the gate oxide layers by using the photoetching and etching methods. According to the invention, a problem that a breakdown voltage is reduced due to electrical field centralization of at the top corner of the trench according to the traditional method can be solved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process, in particular to a method for preparing a trench gate applied to a trench type MOS device. Background technique [0002] In traditional planar MOS (Metal Oxide Semiconductor) devices, the source, gate and drain of the MOS transistors are all located on the horizontal plane of the silicon wafer, which not only occupies a large area, but also has a large on-resistance and power consumption. , unable to meet the requirements of miniaturization and low power consumption of power devices. The trench MOS device cleverly forms the gate of the transistor in the groove perpendicular to the surface of the silicon wafer, so that the conduction channel is transferred to the longitudinal direction of the silicon wafer. This has three advantages: (1) Reduce the device area , to further increase the integration density of the device, (2) effectively reduce the on-resistance and power ...

AI Technical Summary

Problems solved by technology

[0004] The technical problem solved by the present invention is to provide a method for preparing a trench gate applied to a trench MOS device. By increasing the thickness of the gate oxide layer at the apex of the trench, the breakdown voltage there is increased to the same level as that of the trench. Comparable or even higher level of sidewall and bottom to solve the problem of lower breakdown voltage due to easy concentration of electric field at the top corner of the trench in conventional methods

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