Power transistor of double-gate MOS structure and manufacturing method of power transistor

Abstract

The invention relates to a power transistor of a double-gate MOS structure. A gate oxidation layer is located on a first doping layer. A second doping layer is located inside the first doping layer and connected with the gate oxidation layer. A third doping layer is located inside the second doping layer and connected with the gate oxidation layer. An insulating dielectric layer covers a polycrystalline silicon layer of an active area primitive cell. A metal layer covers the insulating dielectric layer and extends into a lead hole of the active area primitive cell and is communicated with the third doping layer and the second doping layer. The polycrystalline silicon layer of the active area primitive cell comprises a first polycrystalline silicon gate and a second polycrystalline silicon gate, wherein the first polycrystalline silicon gate and the second polycrystalline silicon gate are isolated from each other by an insulating dielectric layer and are not connected with each other, and the first polycrystalline silicon gate and the second polycrystalline silicon gate are connected to corresponding gate electrode welding areas through metal leads respectively so as to be controlled respectively. The power transistor of the double-gate MOS structure is simple in structure, the polycrystalline silicon layer is divided into the two polycrystalline silicon gates capable of being controlled respectively, the current channel density can be flexibly controlled, and the power transistor can reach the optimum performance state.

Description

technical field [0001] The invention relates to a power transistor with a double-gate MOS structure and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background technique [0002] In the manufacturing process of conventional MOSFET, IGBT, MCT and other power semiconductor devices, the original cell structure of the source region is as shown in figure 1 As shown, the gate oxide layer 4 is formed after the gate oxide treatment is performed on the first doped layer 3, and then the polysilicon layer 5 is deposited on the gate oxide layer 4, and then the polysilicon layer 5 is photolithographically etched to form the first window, Ions are implanted in the first window and diffused to form the second doped layer 2, and then the ions are implanted and diffused to form the third doped layer 1, and then the insulating dielectric layer 6 is deposited, and the lead hole 8 is photolithography, and finally deposited Metal layer 7. [0003] ...

AI Technical Summary

Problems solved by technology

However, after the chip is fabricated, the width H of the polysilicon gate in the active region and the spacing L between the polysilicon gates will not change again. When the width H of the polysilicon gate in the active region and the spacing L between it are constantly increased, it will inevitably be The current channel density in the active area decreases, that is, the current density of the device decreases, and the voltage drop of the device designed in this way will increase, which will increase the static loss of the device during application.

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