Three-dimensional quantum well transistor and forming method thereof
A quantum well and transistor technology, applied in the field of three-dimensional quantum well transistors and their formation, can solve problems such as poor thermal stability and affect device performance, and achieve the effects of improving performance and thermal stability, increasing contact area, and increasing length
Active Publication Date: 2014-07-09
SEMICON MFG INT (SHANGHAI) CORP
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[0004] However, high electron mobility transistors usually affect device performance due to their poor thermal stability
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[0032] As mentioned in the background art, the thermal stability of existing high electron mobility transistors (HEMTs) is not high, which affects the performance of the transistors.
[0033] The technical solution of the present invention proposes a three-dimensional quantum well transistor and its forming method. On the surface of the fin formed by the insulating buffer layer, a quantum well layer, a barrier layer, and a layer located on the surface of the barrier layer and across the fin are sequentially formed. grid structure. The quantum well layer and the potential barrier layer constitute the heterojunction of the transistor and cover the surface of the fin. The technical scheme of the invention can increase the area of the channel region of the transistor, improve the performance of the transistor, increase the thermal conductivity between the channel region and the substrate, and improve the thermal stability of the transistor.
[0034] In order to make the above o...
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The invention discloses a three-dimensional quantum well transistor and a forming method of the three-dimensional quantum well transistor. The forming method of the three-dimensional quantum well transistor comprises the steps that a semiconductor substrate is provided; a buffer layer is formed on the surface of the semiconductor substrate; the buffer layer is etched, so that a fin portion is formed; an insulating layer is formed on the surface of the semiconductor substrate; a quantum well layer is formed on the surface of the fin portion; a barrier layer is formed on the surface of the quantum well layer; a gate structure which stretches over the fin portion is formed above the barrier layer, wherein the gate structure comprises a gate dielectric layer located on the surface of the barrier layer and a grid electrode located on the surface of the gate dielectric layer; side walls are formed on the two sides of the gate structure; source electrodes and drain electrodes are formed on the gate structure and located on the portions, on the two sides of the side walls, of the fin portion. By the adoption of the forming method of the three-dimensional quantum well transistor, the performance and the thermostability of the transistor can be improved.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a three-dimensional quantum well transistor and a forming method thereof. Background technique [0002] In a common MOS device, the channel region is formed by doping the semiconductor substrate, and the majority carriers and ionized impurities coexist, and the majority carriers will be scattered by the ionized impurities during the migration process, so that The mobility of carriers decreases and the performance of devices decreases. Moreover, as the size of semiconductor devices continues to shrink, the short-channel effect seriously affects the performance of transistors. [0003] The channel region of a high electron mobility transistor (HEMT) is formed by a heterojunction consisting of an undoped quantum well layer and a barrier layer located on the surface of the quantum well layer, which exists in the quantum well The two-dimensional electron gas that migrates in ...
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IPC IPC(8): H01L21/335H01L29/778
CPCH01L29/66462H01L29/7783
Inventor 肖德元
Owner SEMICON MFG INT (SHANGHAI) CORP