A kind of preparation method of active region

Abstract

The invention provides an active region manufacturing method and a semiconductor device manufacturing method. The active region manufacturing method includes the steps that firstly, plasma processing is conducted on the edge area of a wafer to remove photoresist and / or residues of a bottom anti-reflection coating on the edge area; secondly, the bottom anti-reflection coating is etched through gas with the high etching selection ratio of the bottom anti-reflection coating relative to a lower layer thin film below the bottom anti-reflection coating. Thus, it is ensured that the edge area of the wafer and the pattern area of the wafer have the same thin film thickness in the subsequent processes, and an oxidation film with the uniform thickness is formed in the subsequent contact hole manufacturing process. According to the active region manufacturing method, the reaction gas used for processing the edge area is improved, and therefore the defect that the key size of the pattern area is easily reduced in an existing process is overcome; thus, when the active region manufacturing method is used, the problem that an adhesive coating is stripped off in the contact hole manufacturing process can be solved, and quality of the device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an active region preparation method capable of reducing peeling defects of an adhesive layer in a subsequent contact hole preparation process. Background technique [0002] In the manufacturing process of semiconductor devices, the preparation process of active devices generally includes: preparation of gate, preparation of active area (AA loop), deposition of interlayer dielectric layer, preparation of contact holes (CT loop), etc. Among them, the preparation process of the contact hole usually includes: first, film deposition is carried out on the device substrate (wafer), and the deposited film material can be an inorganic dielectric material; then, a photoresist and a bottom anti-reflection layer are coated, Using the photolithography process, pattern the photoresist (CT Photo), use the patterned photoresist as a mask, and use the etching process to etch the CT structu...

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Problems solved by technology

[0015] At present, the main method in the industry to reduce glue layer lift-off defects is to perform plasma treatment on the edge of the wafer after APF deposition or etching of the shallow trench isolation structure in the active region preparation process to achieve the removal of the edge of the wafer. Photoresist or BARC residue problem. However, the currently used processing gas contains F, which cannot control the etching rate and selectivity ratio of oxide, SiN, and Si, so that the consistency of the thickness of the oxide film on the edge of the wafer cannot be guaranteed; and, In the subsequent contact hole etching, under the condition of increasing the etching window, it is easy to cause further loss of the oxide film on the edge of the wafer. Using this method, it will still cause gluelayer peeling defects

[0016] In addition, there is another method to reduce glue layer lift-off defects, which uses O after patterning photoresist 2 To deal with the photoresist or BARC residue on the edge of the wafer, although the residue can be cleaned up, but when etching BARC, the etching selectivity of BARC relative to the oxide film is too small, because the material of BARC is relatively soft, in The BARC at the edge of the wafer will be relatively thick, which will easily cause the oxide film of the next layer to be etched in the center of the wafer or in the pattern area, while the BARC is still being etched in the edge area of ​​the wafer; thus, when When the etching of the pattern area is completed, there may still be SiN residues in the edge area of ​​the wafer. In the subsequent process, some defects will appear in the film deposited on the SiN residues. For example, the TiN film deposited on the SiN residues will have peeling defects.

At the same time, due to the use of O 2 During the process, if the process parameters such as reaction pressure are not properly controlled, it is easy to cause the critical dimension of the wafer pattern area to shrink (shrink)

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