Decoupling capacitor structure in integrated passive device (IPD) and manufacturing method of decoupling capacitor structure
A technology for integrating passive devices and decoupling, which is applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., and can solve problems such as unfavorable signal integrity design, signal interference of packaging substrate PCB boards, and unfavorable device miniaturization.
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[0055] In order to solve the problems in the prior art, the present invention provides a method for preparing a decoupling capacitor in an integrated passive device, including: providing a semiconductor substrate as the lower plate of the decoupling capacitor, in the semiconductor substrate Doped with ions;
[0056] forming a hard mask layer on the semiconductor substrate, etching the semiconductor substrate to form trenches in the semiconductor substrate to define the decoupling capacitor region;
[0057] Depositing a dielectric layer in the trench as a dielectric layer of the decoupling capacitor;
[0058] Filling the trench with a conductive material as the upper plate of the decoupling capacitor;
[0059] forming a contact hole on the upper plate to electrically connect the decoupling capacitor;
[0060] An integrated passive device is formed on the contact hole, and an electrical connection is formed with the decoupling capacitor through the contact hole, so as to reali...
Embodiment 1
[0071] Attached below Figure 2a-2h The first embodiment of the structure of the decoupling capacitor in the integrated passive device of the present invention will be further described.
[0072] First, a semiconductor substrate 201 is provided, and ion doping is performed on the semiconductor substrate 201 .
[0073] Specifically, in the present invention, the semiconductor substrate 201 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc., other active devices can also be formed in the semiconductor substrate.
[0074] In the present invention, the substrate can be P-type or N-type, and in this embodiment, the substrate is a P-type substrate.
[0075] Next, perform ion doping on the semiconductor substrate 201, specifically, perform N-type doping on the surface of the P-type substrate, ...
Embodiment 2
[0119] Combine below Figures 3a-3c Another embodiment of the present invention will be further described.
[0120]In this embodiment mode, a semiconductor substrate 201 is first formed, and the semiconductor substrate 201 is ion-doped to form a hard mask layer on the semiconductor substrate 201; using the hard mask layer as a mask , etch the semiconductor substrate 201, form a trench 20 in the semiconductor substrate 201 to define the decoupling capacitor region; fill the trench 20 with a doped sacrificial oxide layer 206, and then perform Diffusion step, stripping and removing the sacrificial oxide layer 206; Figure 2e pattern shown. The forming step can refer to the method in Example 1, but is not limited to this method.
[0121] Then step 301 is executed to fill the trench 20 with a doped semiconductor material 213 .
[0122] Specifically, refer to Figure 3a In this step, the doped semiconductor material 213 is selected as the upper plate of the decoupling capacitor...
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