A complex programmable logic device with enhanced asynchronous clock management

Abstract

The invention discloses a complex programmable logic device enhancing asynchronous clock management and relates to the technical field of programmable logic devices. A delay locked loop (DLL) and n variable delayers connected with the DLL are integrated in the device, and n is an integer not smaller than 1; the DLL generates one path of first clock signals and n paths of phase delay codes, the phase delay codes correspond to the variable delayers in a one-to-one mode, and the variable delayers carry out phase shift on received second clock signals according to the corresponding phase delay codes and transmit the received second clock signals to logic units of the complex programmable logic device. The complex programmable logic device can provide different clock signals to the logic units of the CPLD, CPLD delay compensation, clock regulation, phase adjustment and different phase shift functions of multiple synchronous or asynchronous clocks are increased, the application field of the CPLD is widened to digital information reading, circuit design and system integration are simplified, power consumption is lowered, development cost and material cost are reduced, and use is convenient.

Description

technical field [0001] The invention relates to the technical field of programmable logic devices, in particular to a complex programmable logic device that strengthens asynchronous clock management. Background technique [0002] Programmable logic devices refer to all digital integrated circuits that can be configured and changed by software means to change the internal connection structure and logic units of the device to complete the established design functions. Commonly used programmable logic devices mainly include simple logic array (PAL / GAL), complex programmable logic device (CPLD) and field programmable logic array (FPGA). [0003] refer to figure 1 , The structure of the CPLD is mainly composed of programmable logic units surrounding the central programmable interconnection matrix unit (that is, the "wiring pool, wiring matrix" in the figure). Wherein, the logic unit has a plurality of logic macrocells (MacroCell), and the structure of the logic macrocell is rel...

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Problems solved by technology

[0006] The technical problem to be solved in the present invention is: how to overcome the clock instability and phase offset accumulation problems when integrating PLL in CPLD

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