Mask read only memory and manufacturing method thereof
A read-only memory and model technology, which is applied in the manufacture of mask read-only memory and the field of mask read-only memory, can solve the problems of reducing device integration, increasing device area, and small array area, so as to reduce leakage and isolation effects Good, the effect of reducing the area
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[0047] Such as image 3 Shown is a cross-sectional view of the NMOS memory cell of the mask read-only memory of the embodiment of the present invention; Figure 4 Shown is the layout of the mask type read-only memory of the embodiment of the present invention. The mask type read-only memory of the embodiment of the present invention is formed on a silicon substrate 201, a shallow trench field oxide 2 isolation structure is formed on the silicon substrate 201, and a plurality of active sources are isolated by the shallow trench field oxide 2 Area 3; the array structure of the mask read-only memory includes a plurality of longitudinally arranged bit lines BL, a plurality of laterally arranged word lines WL, and a plurality of laterally arranged ground lines GND; Figure 4 The CCP has shown 8 bit lines BL, namely BL(0), BL(1), BL(2), BL(3), BL(4), BL(5), BL(6) and BL(7), Seven bit lines WL, namely WL(0), WL(1), WL(2), WL(3), WL(4), WL(5) and WL(6), and four ground lines GND.
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