Method of forming a semiconductor device

Abstract

The invention discloses a forming method of a semiconductor device. The forming method comprises the following steps: providing a substrate, wherein discrete supporting parts and a nanowire suspended on the surface of a first dielectric layer are arranged on the surface of the substrate, and the two ends of the nanowire are respectively connected with the side walls of the adjacent supporting parts; forming a pseudo-grid membrane on the surface of the nanowire; adopting an anisotropic dry etching process to etch the pseudo-grid membrane and the nanowire until the first dielectric layer is exposed, enabling the pseudo-grid membrane to form a pseudo-grid electrode layer, and enabling the nanowire to form a nanowire channel structure encircled by the pseudo-grid electrode layer; adopting a selective deposition process to form a nanowire source / drain structure between the side wall of the nanowire channel structure and the side walls of the supporting parts; forming a second dielectric layer on the surfaces of the first dielectric layer, the pseudo-grid electrode layer and the nanowire source / drain structure, and enabling the surface of the second dielectric layer to be flush with the surface of the pseudo-grid electrode layer; then, removing the pseudo-grid electrode layer, and forming a gate structure in the opening. The formed semiconductor device is accurate in size and stable in performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. Transistors, as the most basic semiconductor devices, are currently being widely used. Therefore, as the component density and integration of semiconductor devices increase, the gate size of transistors is also getting shorter and shorter. However, the shortening of the gate size of the transistor will cause the short-channel effect of the transistor, thereby generating leakage current, and ultimately affecting the electrical performance of the semiconductor device. [0003] In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fully surrounded gate nanowire ...

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Problems solved by technology

[0006] However, the gate-all-around nanowire transistors formed by the prior art are poorly formed

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