Semiconductor device forming method

Abstract

A semiconductor device forming method comprises providing a substrate which comprises a core region and a peripheral region, wherein shallow groove isolation layers and a plurality of fins higher than the shallow groove isolation layers are formed on the substrate; forming a cap layer material layer on the substrate, wherein the substrate and fin surfaces are covered with the cap layer material layer; removing the part of the cap layer material layer in the peripheral region, and using the remaining cap layer material layer in the core region as a cap layer; forming a first etching blocking layer on the surfaces of the fins in the peripheral region through a peripheral region process after the cap layer is formed. In the core region, the cap layer blocks the diffusion of oxygen to the fin surfaces, and the silicon consumption on the fin surfaces in the core region is small or not consumed fundamentally. Compared with the prior art, the fin line width in the core region and the expected line width are of little difference or nearly equal, and accordingly, the high carrier mobility of carriers in fins of a core circuit can be guaranteed, and the core circuit has high signal transmission rate.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor device. Background technique [0002] In the field of semiconductor technology, usually an integrated circuit on a wafer includes a core circuit and I / O circuits around the core circuit. The fin field effect transistor is used in the manufacturing process of integrated circuits due to its advantages of small size and large driving current. [0003] The prior art is to form FinFETs using a gate-last process. The fin field effect transistor includes: a fin on the base; a metal gate across the fin; the fins on both sides of the gate are heavily doped, serving as source and drain respectively. [0004] refer to figure 1 , using a self-aligned double patterning (Self-aligned Double patterning, SADP for short) method to form a plurality of fins 2 arranged side by side on the substrate 1 . The fins 2 of the core area I and the fins 2 of th...

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Problems solved by technology

However, during the thermal oxidation growth process, the silicon on the surface of the fin portion 4 is depleted.

refer to figure 2 , image 3 , the fin 4 line width W after thermal oxidation growth 2 Less than the line width W of fin 4 before thermal oxidation growth 1 , the surface loss of the fin part 4 in the core area I reduces the line width of the fin part 4, which will reduce the signal transfer rate of the core circuit

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