Gate dielectric layer forming method and MOS transistor forming method

Abstract

Provided are a gate dielectric layer forming method and a MOS transistor forming method. The gate dielectric layer forming method comprises: providing a first semiconductor substrate; forming an interfacial layer on the first semiconductor substrate; forming a metallic layer on the interfacial layer; forming a high-K dielectric layer on the metallic layer; and performing annealing treatment, wherein the part, in contact with the first semiconductor substrate, of the interfacial layer is reduced to silicon and forms a second semiconductor substrate along with the first semiconductor substrate such that the interfacial layer is thinned. The gate dielectric layer forming method may reduce EOT (Equivalent Oxide Thickness) and the interfacial layer formed by the method has better density and uniformity. As a result, the gate dielectric layer formed by the method has a larger dielectric constant than that with same thickness in the prior art and a corresponding semiconductor structure is improved in performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a gate dielectric layer and a method for forming a MOS transistor. Background technique [0002] With the reduction of semiconductor process technology nodes, the metal-oxide-semiconductor Field-Effect-Transistor (MOSFET, hereinafter referred to as MOS) of the traditional silicon dioxide gate dielectric layer and polysilicon gate electrode layer Transistor) devices suffer from increased leakage and gate layer depletion. In order to solve these problems, it is proposed in the prior art to use a high K (high K, HK) material instead of silicon dioxide to make a gate dielectric layer, that is, a high K dielectric layer, and to use a metal material instead of polysilicon to make a gate electrode layer (metal gate, MG), that is, the metal gate, this structure is referred to as HKMG. [0003] However, the disadvantage of using the high-K dielectric layer...

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Problems solved by technology

[0010] However, it is very difficult to directly form an interface layer 110 with a smaller thickness and better quality.

The quality of the interface layer 110 formed by the existing method is usually poor, resulting in a decrease in the performance of the MOS transistor

In addition, in the formation process of the gate dielectric layer, an annealing process must usually be used, and the annealing process will cause the interface layer 110 to be oxidized and cause its thickness to increase, further exacerbating the degradation of the performance of the MOS transistor.

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