Calibrating module for sampling time error of TIADC (Time-interleaved Analog To Digital Converter) and calculating method for calibrating module

Abstract

The invention discloses a calibrating module for the sampling time error of a TIADC (Time-interleaved Analog To Digital Converter). The TIADC comprises a data conversion module and a data composition module, wherein the data conversion module consists of M channels comprising M sample hold circuits and M sub channel ADCs (Analog To Digital Converter); a reference channel is arranged on the data conversion module in parallel, so that a data conversion module with the reference channel is formed; the reference channel is formed by connecting one sample hold circuit with one single-bit reference channel ADC in series; the calibrating module is arranged between the data conversion module with the reference channel and the data composition module and consists of M auto-correlation operation modules, a memory, (M-1) differential modules and (M-1) error compensation modules. The calibrating module disclosed by the invention is suitable for calibrating TIADC systems of any channel and signals within the whole Nyquist sampling frequency, simply acquiring relative sampling time error among all the channels and efficiently compensating the relative sampling error, so that the calibration of the time error among the channels can be quickly and accurately realized at lower hardware overhead.

Description

technical field [0001] The invention relates to the field of analog-to-digital conversion, and more specifically relates to a calibration module and a calibration algorithm for sampling time errors of multi-channel time-interleaved analog-to-digital converters. Background technique [0002] Modern electronic systems such as communication systems, radar, and image / video processing require high-speed, high-precision analog-to-digital converters. Traditional single-channel analog-to-digital converters will face physical limitations to achieve high speed while ensuring high precision, especially with the development of deep submicron CMOS technology to lower power supply voltage and smaller feature size, the use of traditional The design of high-precision, high-speed analog-to-digital converters of the structure becomes more and more difficult. [0003] The multi-channel time-crossed ADC can break through the limitations brought by process factors through parallel acquisition t...

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Problems solved by technology

The correlation-based algorithms proposed by S.Jamal and D.Fu et al. (Jamal Shafiq M, Fu Daihong, Hurst Paul J, Lewis Stephen H.A 10-b120-Msample / s time -interleaved analog-to-digital converter with digital background calibration[J].IEEE Journal of Solid-State Circuits,v 37,n 12,p 1618-1627,December 2002), however, this scheme is only applicable to two-channel TIADC , cannot be extended to more channels or even arbitrary channels

Chung-Yi Wang and Jieh-Tsorng Wu et al proposed to do zero detection between channels to extract the error between channels (“A Background Timing-Skew Calibration Technique for Time-Interleaved Analog-to-Digital Converters” Chung-Yi Wang ,Student Member,IEEE,and Jieh-Tsorng Wu,Member,IEEE), however, this scheme has high requirements for the frequency of the input signal

Roger Petigny and Hugo Gicquel et al. proposed to add a reference channel with a sub-channel accuracy similar to TIADC for calibration ("Background Time Skew Calibration for Time-Interleaved ADC Using Phase Detection Method"), however, this solution requires a reference channel Relatively high, high hardware consumption

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