III-V clan nano wire planar transistor based on SOI substrate and preparation method thereof

Abstract

An III-V clan nano wire planar transistor based on a SOI substrate and a preparation method thereof; the transistor comprises the following elements: the SOI substrate; a source zone and a drain zone formed on the SOI substrate; a plurality of III-V clan nano wires connected with the source zone and the drain zone; a SiO2 buffer layer formed on surfaces of the source zone and the drain zone; an insulation medium layer formed on surfaces of the III-V clan nano wires and the SiO2 buffer layer, and completely wrapping the III-V clan nano wires; a source electrode formed on the top of the soruce zone; a drain electrode formed on the top of the drain zone; a grid electrode formed on the plurality of III-V clan nano wires between the source zone and the drain zone, and wrapping the plurality of III-V clan nano wires. The preparation of plane nano wire transistors can be realized.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor devices, in particular to a III-V group nanowire planar transistor based on an SOI substrate and a preparation method thereof. Background technique [0002] Silicon-based III-V transistors can use higher mobility to obtain higher drive current at lower drive voltage, making their processing speed three times higher than before, or reducing their power consumption to 1 / 10 of the original, This is conducive to the acquisition of high frequency, low power consumption devices. However, due to the lattice mismatch, thermal expansion coefficient mismatch and crystal structure difference between silicon and III-V materials, the resulting dislocations make the heterogeneous integration of the two difficult. By vertically growing III-V nanowires, the contact area with silicon can be reduced, and the nanowires can release the lattice mismatch stress and thermal mismatch from the two dim...

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Problems solved by technology

In order to facilitate the logic wiring of the gate and the preparation of the planar process, a horizontal nanowire structure is usually required, but the vertical nanowire structure needs to be artificially transferred to obtain a horizontal structure, such as ultrasonic vibration of the vertical nanowire in a high-concentration ethanol solution , the shaken-off nanowires also need to use electron beam exposure and other methods to position the electrodes, which is not conducive to the preparation of large areas

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