Method for preparing nickel silicide

Abstract

The invention discloses a method for preparing nickel silicide. TiN layers with opposite stress are deposited on an NMOS (N-channel metal oxide semiconductor) and a PMOS (P-channel metal oxide semiconductor) to serve as cap layers of NiPt; different stresses are memorized after reaction and phase change in the follow-up nickel silicide formation process, so that the formed nickel silicide can apply pull stress to NMOS channels and PMOS channels, negative effects caused by introduction of the stress layers are avoided in the formation process of metal silicide, and the performance of devices is improved; NiPt covering the NMOS and the PMOS contains Pt with different content and can meet different requirements of the devices; besides, the SiN reserved on the NMOS can be used for removing NiPt on the NMOS, and additional damage to S / D (source / drain) is avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, and more specifically, to a method for making nickel silicide. Background technique [0002] In semiconductor manufacturing technology, metal silicide is widely used in source / drain contacts and gate contacts to reduce contact resistance due to its low resistivity and good adhesion with other materials. Metals with high melting points such as Ti, Co, Ni, etc. can react with silicon to form metal silicides with low resistivity through one-step or multi-step annealing process. With the continuous improvement of the semiconductor process level, especially at the technology node of 45nm and below, in order to obtain lower contact resistance, nickel and nickel alloys (such as NiPt) have become the main materials for forming metal silicides. [0003] As the miniaturization of the feature size of VLSI continues, the size of field effect transistors is also getting...

AI Technical Summary

Problems solved by technology

[0006] However, the above-mentioned existing Ni silicide formation process does not adjust NMOS and PMOS respectively, and adopts TiN with a single stress to cover the NMOS and PMOS as a protective layer of NiPt, and a single stress (tensile stress or compressive stress) Stress) TiN can only contribute to the improvement of electron mobility or hole mobility of one of NMOS or PMOS, but in the case of benefiting one of them, it will be detrimental to the electrical performance of the other device influences

In addition, depositing NiPt metal layers with the same thickness and Pt content on NMOS and PMOS devices does not take into account how to meet the requirements of different devices

[0007] Therefore, the existing Ni silicide formation process does not take into account the negative effects brought by the TiN stress layer introduced during the formation of metal silicide, and how to meet the requirements of different devices, it needs to be optimized

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