The manufacturing process of sonos memory

Abstract

The invention discloses a manufacturing process method of a SONOS memory. The manufacturing process of the cell structure comprises the following steps: forming an ONO layer of a memory cell tube and a gate silicon oxide layer of a selector tube; depositing a polysilicon layer and performing photoetching to form Polysilicon gate; perform HF wet etching process to remove silicon oxide outside the polysilicon gate and form an undercut at the bottom edge of the polysilicon gate; perform thermal oxidation process to increase the thickness of the gate dielectric at the bottom edge of the polysilicon gate; perform HALO ion implantation and LDD ion implantation ; The LDD doping concentration of the memory cell tube is reduced by utilizing the blocking effect of the bottom two layers of the ONO layer. The invention can reduce electric leakage, improve reliability, and has lower cost.

Description

technical field [0001] The invention relates to a manufacturing process method of a semiconductor integrated circuit, in particular to a manufacturing process method of a SONOS memory. Background technique [0002] The cell structure of silicon-oxide-nitride-oxide-silicon (Silicon-Oxide-Nitride-Oxide-Silicon, SONOS) memory includes a storage unit (cell) tube and a selector tube, and the gate dielectric layer of the two devices is in The vertical electric field strength that the memory bears during operation is greater than that of the CMOS device, so both devices have a large GIDL leakage current. The channel of the cell tube of the SONOS memory has been doped with a higher concentration of N-type impurities to form a depletion tube, and the doping concentration of the lightly doped drain (LDD) required by the cell tube is lower than that of the select tube. However, the selection tube and the cell tube share LDD and HALO ion implantation, and the LDD doping of the two tube...

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Problems solved by technology

[0004] Depend on figure 1 It can be seen that since the channel region 107 of the cell tube 101 is N-type doped, the formation of the LDD region 108a superimposed on the channel region 107 will make the LDD doping concentration of the cell tube 1001 too high, in addition to causing GIDL leakage and channel In addition to channel leakage, it will also cause disturbance (disturb) due to the strong vertical electric field in the SONOS dielectric layer

However, the gate dielectric layers 104 and 105 of the two devices bear greater vertical electric field strength than the CMOS device when the memory is working, so both devices have a large GIDL leakage current

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