Analysis method of total dose effect sensitivity of logic gate circuit and analysis method of total dose effect sensitivity of CMOS digital circuit

Abstract

The invention relates to an analysis method of a total dose effect sensitivity of a logic gate circuit and an analysis method of a total dose effect sensitivity of a CMOS digital circuit. The analysis method of the total dose effect sensitivity of the logic gate circuit comprises 1) listing a working state of a to-be-analyzed logic gate circuit in an irradiation process, listing a working state of the to-be-analyzed logic gate circuit in a test process, and performing permutation and combination on the working states in the two processes to form multiple groups of input signal combinations, 2) simplifying a specific structure of a pMOS tube combination and a specific structure of an nMOS tube combination which form the logic gate circuit, and enabling the specific structure of the pMOS tube combination and the specific structure of the nMOS tube combination to be equivalent to structure forms of phase inverters, and 3) calculating electric conductance of the various phase inverters, wherein a combination of the minimum equivalent pMOS tube electric conductance and the maximum equivalent nMOS tube electric conductance corresponds to the strongest total-dose sensitivity. The method capable of rapidly identifying total-dose effect sensitive nodes in a circuit achieves identification of the total-dose effect sensitive nodes in the circuit during the design phase, and then can be used to guide reinforcing design and greatly save the layout area.

Description

technical field [0001] The invention belongs to the research field of total dose effect of CMOS digital integrated circuits. Background technique [0002] Semiconductor device circuits working in the space radiation environment for a long time will be affected by the total dose effect, which is specifically characterized by the degradation of the electrical performance of the device or circuit or even functional failure. [0003] Common methods for total dose hardening of circuits can be divided into three categories: layout hardening, design hardening, and shield hardening. Layout reinforcement refers to the adjustment of the most basic unit, such as changing the ion implantation in the process flow, changing the position or number of well contacts, changing the layout structure of a single tube, etc., see patent application number 201010548221.4, "An anti-total dose radiation hardened transistor structure", etc. Design hardening refers to adjustments at the netlist level...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the lack of existing methods for identifying sensitive areas of CMOS circuits, the existing reinforcement methods do not perform the identification of sensitive areas before the total dose of the circuit is strengthened, resulting in the increase of layout area and the reduction of indicators such as integration, the present invention provides a The analysis method for the sensitivity of the total dose effect of logic gate circuits and CMOS digital circuits can identify the sensitive nodes of the total dose effect, which can be used to guide the reinforcement design and obtain the balance between cost and radiation resistance performance

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