Preparation method of semiconductor field effect transistor device with three-dimensional gate-all-around structure

Abstract

The present invention provides a preparation method of a semiconductor field effect transistor device with a three-dimensional gate-all-around structure. A self-support three-dimensional micro-nano functional structure is taken as a carrier, and a micro-nano processing technology is employed to prepare the semiconductor field effect transistor device with the three-dimensional gate-all-around structure. The preparation method provided by the invention specifically comprises the following steps: a first dielectric layer is prepared on the surface of the self-support three-dimensional micro-nano functional structure; a three-dimensional gate-all-around metal electrode is prepared on the first dielectric layer; a second dielectric layer is prepared on the three-dimensional gate-all-around metal electrode to ensure electrical isolation of metal leads of a source electrode and a drain electrode and a grid; an electrode contact hole is prepared through etching on the second dielectric layer; and an electrode contact block is prepared and is connected with the electrode contact hole. The transistor device prepared by the method provided by the invention has effective grid-control characteristic, is able to isotropically regulate the field effect between a source electrode and a drain electrode and restrain a wall and corner effect; and moreover, a long and wide channel and smaller drain terminal parasitic capacitance are provided in the micro-nano grade so that the electric field diffusion of the drain terminal is reduced and the performance of the transistor device may be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preparing a three-dimensional gate-around-structure semiconductor field-effect transistor device. Background technique [0002] With the further development of electronic integration technology, the demand for miniaturization and high efficiency of electronic devices is gradually increasing. However, as the size of semiconductor devices continues to shrink, the method of improving device performance by proportionally reducing device size is approaching the limit. The channel effect and subthreshold performance degradation also limit the further reduction of device size, so more and more researchers pay attention to the use of transistors with complex geometric gate structures to increase the current control of the gate to the transistor channel. Among all the multi-gate structures proposed so far, the ring gate has the advantages of better chip area reduction,...

AI Technical Summary

Problems solved by technology

However, for self-supporting functional micro-nano materials, how to effectively prepare three-dimensional gate-all-around devices without shifting the position of the supporting substrate still requires innovation and development in methods and technologies

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