Test structure and test method

Abstract

The invention provides a test structure. The test structure comprises a substrate layer and a plurality of discrete first inter-layer metal layers, wherein the first inter-layer metal layers are in electrical connection with a plurality of first contact plugs; and the test structure further comprises a continuously distributed second inter-layer metal layer, wherein the second inter-layer metal layer is in electrical connection with the first inter-layer metal layers through a plurality of second contact plugs. According to the invention, the first inter-layer metal layers are connected to a big second inter-layer metal layer through the second contact plugs, thus, the effect of grounding is realized, and potential difference of the surface of the first contact plugs after the metal is in broken line connection is enhanced; and based on the principle of voltage contrast of a scanning electron microscope, light and shade degree of the first contact plugs can be observed from the back of a wafer so as to reflect whether the first contact plugs are contacted well with the first inter-layer metal layers, thus, locations of defect can be found quickly, process defects can be reflected, and the aim of early defect monitoring is realized.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and relates to a test structure and a test method. Background technique [0002] As the density of chip devices increases, the size of metal wiring becomes smaller and smaller, and the aspect ratio of metal etching becomes larger and larger. Underetch of the metal layer is prone to occur, resulting in yield loss. [0003] During the semiconductor chip manufacturing process or when the manufacturing is completed, it is necessary to test the parameters related to the semiconductor chip to monitor whether the produced semiconductor chip meets the process requirements and whether the yield rate is qualified, etc. The test of the relevant parameters is usually through setting and cutting. It is done by the test structure (TestKey) of the channel area. In the test structure design, there will be a contact chain (CTchain) on the chip to monitor the connection between CT (contact, contact) and...

AI Technical Summary

Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a test structure and a test method for solving the problem that there is no effective method in the prior art to directly locate the disconnected connection position of the contact plug, or the defect cannot be quickly located location, the problem of inability to realize early failure location

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