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An N-type, well region technology, applied in transistors, electrical components, electric solid state devices, etc., can solve the problems of reducing the resistance of the drift region, affecting the stability of the power electronic system, and the device cannot be turned on normally, so as to improve the turn-off characteristics. , The effect of suppressing the snapback phenomenon, improving the off-state characteristics and anti-latch ability
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Embodiment 1
[0031] Such as image 3 As shown, this example includes an N-type substrate 1, a dielectric layer 2 located on the upper surface of the N-type substrate, and an N-type drift region 3 located on the upper surface of the dielectric layer 2; one end of the upper layer of the N-type drift region 3 has a P-type well Region 4, the other end of which has an N-type well region 5; the upper layer of the P-type well region 4 has a P+ body contact region 8 and an N+ cathode region 9, and the P+ body contact region 8 and N+ cathode region 9 are juxtaposed along the lateral direction of the device set, and the N+ cathode region 9 is located on the side close to the N-type well region 5; the upper surface of the P-type well region 4 between the N+ cathode region 9 and the N-type drift region 3 has a gate structure; the N-type The upper layer of the well region 5 has a P+ anode region 10 and an N+ anode region 11, the P+ anode region 10 and the N+ anode region 11 are arranged side by side al...
Embodiment 2
[0036] Such as Figure 4 As shown, the basic structure of this embodiment is the same as that of Embodiment 1, the difference is that the width of the P+ anode region 10 along the lateral direction of the device is greater than the width of the N+ anode region 11 along the lateral direction of the device, and a=b at the same time, in the P+ anode region and the N+ There is an N-type high-resistance area in the gap of the anode area. The N-type high-resistance region appearing in this example and the following embodiments means that a certain concentration of P-type impurities is compensated and injected into the original N-type well region to make it an N-type high-resistance region.
[0037] In addition to the beneficial effects described in Embodiment 1, this example can also significantly increase the distributed resistance of the electron current flowing on the PN junction formed by the P+ anode region and the N-type high-resistance region, thereby making it easier to supp...
Embodiment 3
[0039] Such as Figure 5 , the basic structure of this embodiment is the same as that of Embodiment 2, the difference is that the distance between the first P+ anode region and the second P+ anode region near the P-type well region 4 is a, and the distance between the N+ anode region 11 side The spacing is c (opening 13 in the figure), and a
[0040] This embodiment can also increase the distribution resistance of the electron current flowing on the PN junction formed by the P+ anode region and the N-type high resistance region, thereby suppressing the snapback phenomenon at the initial stage of device conduction.
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