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A method for integrating vertical nanowire transistors

An integration method and nanowire technology, applied in nanotechnology, nanotechnology, nanotechnology for information processing, etc., can solve problems such as difficulty in using the gate-last process, limit the improvement of device performance, etc., to avoid etching damage, The effect of improving consistency and improving performance

Active Publication Date: 2018-02-13
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] This integration scheme is difficult to use the gate-last process, which limits the improvement of device performance;

Method used

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  • A method for integrating vertical nanowire transistors
  • A method for integrating vertical nanowire transistors
  • A method for integrating vertical nanowire transistors

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0094] The CMOS integration of bulk silicon vertical nanowire devices with a diameter of 6nm can be realized according to the following steps (the structural parameters are set according to the High-Performance devices of the "11 / 10nm" technology generation in ITRS-2013):

[0095] 1) On a (100) bulk silicon substrate, a double well (N well / P well), SiO 2 The shallow trench isolation (Shallow Trench Isolation, STI), the surface is planarized by chemical mechanical polishing (Chemical-MechanicalPolishing, CMP), and the substrate surface retains 50nm SiO 2 ,Such as figure 2 shown;

[0096] 2) Form the epitaxial window of the active region under the device by photolithography and anisotropic etching;

[0097] 3) The P+ heavily doped lower active region (as the source / drain terminal of PMOS) is formed on the N well by the epitaxial process of in-situ doping, and the N+ heavily doped lower active region is formed on the P well (as the NMOS source / drain), such as image 3 shown;...

Embodiment 2

[0121]According to the following steps, the hybrid integration of vertical nanowire devices (such as Si-NMOS and Ge-PMOS) with a diameter of 4.5nm of two kinds of material channels on the SOI substrate can be realized (the structural parameters are according to "8 / 7nm" in ITRS-2013 Technology generation High-Performance devices for setting):

[0122] 1) GeSi epitaxy 20nm on the (100) SOI substrate, respectively carry out N+ and P+ doping to form the lower active region of the device (as the source / drain terminal of the device);

[0123] 2) Realize the isolation of the active region under the N / P device by photolithography and etching, such as Figure 19 shown;

[0124] 3) SiO by LPCVD 2 STI is formed, and the surface is planarized by CMP to expose the upper surface of the heavily doped active region;

[0125] 4) Deposit 3nm SiO sequentially by ALD 2 (as SDE mask layer 1, its thickness defines the length of the source-drain extension region SDE of the device is 3nm), 14nm S...

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Abstract

The invention discloses an integration method of a vertical nanowire transistor, which belongs to the field of CMOS ultra large scale integrated circuit (ULSI) field effect transistor logic devices. This method combines patterned epitaxy and sidewall replacement gate to realize vertical nanowire transistor integration. Compared with the existing method of forming vertical nanowire channel by etching, it can precisely control the cross-sectional area and shape of the device channel. The appearance is improved, and the consistency of the characteristics of the device is improved; the etching damage in the channel formation process in the existing method is avoided, and the performance of the device is improved.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit manufacturing, and relates to a method for realizing vertical nanowire transistor integration by combining patterned epitaxy and sidewall replacement gate. Background technique [0002] When the semiconductor device enters the 22nm technology generation, the horizontal channel three-dimensional multi-gate device (Multi-gate MOSFET, MuGFET) represented by the fin field effect transistor (FinFET), with its outstanding short-channel effect suppression ability, highly integrated Density, compatibility with traditional CMOS technology and other advantages, has become the mainstream of semiconductor devices. [0003] However, when moving towards smaller technology nodes, horizontal channel three-dimensional multi-gate devices face challenges such as difficulty in reducing the pitch of contact holes (limiting the increase in integration density), and gate etching on complex t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
CPCH01L21/823807H01L21/823885H01L29/401B82Y10/00B82Y40/00H01L29/4236H01L29/66439H01L29/775H01L29/66666H01L29/7827H01L29/66545H01L29/0676H01L21/823814H01L21/823828H01L21/823878H01L21/823871
Inventor 黎明杨远程陈珙樊捷闻张昊黄如
Owner PEKING UNIV
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