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Silicon-on-insulator (SOI) dual-port static random access memory (SRAM) unit and fabrication method thereof

A manufacturing method and dual-port technology, applied in the fields of electrical components, semiconductor/solid-state device manufacturing, static memory, etc., can solve the problems of large occupied area of ​​SOI dual-port SRAM unit, weak anti-noise ability, poor stability, etc., and achieve suppression of floating body effect, convenient fully customized SRAM chip, and the effect of improving anti-noise ability

Active Publication Date: 2016-04-13
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In view of the above-mentioned shortcoming of the prior art, the object of the present invention is to provide a kind of SOI dual-port SRAM unit and manufacturing method thereof, be used to solve SOI dual-port SRAM unit occupying a large area, poor stability, power leakage in the prior art The problem of high power consumption and weak anti-noise ability

Method used

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  • Silicon-on-insulator (SOI) dual-port static random access memory (SRAM) unit and fabrication method thereof
  • Silicon-on-insulator (SOI) dual-port static random access memory (SRAM) unit and fabrication method thereof
  • Silicon-on-insulator (SOI) dual-port static random access memory (SRAM) unit and fabrication method thereof

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Embodiment 1

[0088] The present invention provides a SOI dual-port SRAM unit, please refer to figure 1 , shown as a schematic diagram of the circuit principle of the SOI dual-port SRAM cell, including:

[0089] The first inverter 1 is composed of a first PMOS transistor 101 and a first NMOS transistor 102;

[0090] The second inverter 2 is composed of a second PMOS transistor 201 and a second NMOS transistor 202;

[0091] The acquisition transistor 3 is composed of a third NMOS transistor 301, a fourth NMOS transistor 302, a fifth NMOS transistor 303 and a sixth NMOS transistor 304; the source of the third NMOS transistor 301 is connected to the first inverter The output end and the input end of the second inverter, the gate is connected to the write word line WL1 of the memory, and the drain is connected to the write bit line BL1 of the memory; the source of the fourth NMOS transistor 302 is connected to the first The output end of the two inverters and the input end of the first invert...

Embodiment 2

[0103] The present invention also provides a method for making an SOI dual-port SRAM unit, comprising the steps of:

[0104] Step S1 is first performed: provide an SOI substrate including a back substrate, an insulating buried layer, and a top layer of silicon in sequence from bottom to top, and form a shallow trench isolation structure in the top layer of silicon to define an active region.

[0105] As an example, such as Figure 8 As shown, six active regions 20a, 20b, 20c, 20d, 20e and 20f are defined, wherein these six active regions 20e, 20a, 20b, 20c, 20d and 20f are arranged in parallel in sequence, and each active region is surrounded by a The shallow trench is filled with an insulating material to form a shallow trench isolation structure. In this embodiment, the insulating material is silicon dioxide.

[0106] Then execute step S2: as Figure 9 As shown, an N well 30, a first P well 40 and a second P well 50 are fabricated in the top silicon according to the posit...

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Abstract

The invention provides a silicon-on-insulator (SOR) dual-port static random access memory (SRAM) unit and a fabrication method thereof. The unit comprises a first phase inverter, a second phase inverter and an acquisition tube, wherein the first phase inverter comprises a first P-channel metal oxide semiconductor (PMOS) transistor and a first N-channel metal oxide semiconductor (NMOS) transistor, the second phase inverter comprises a second PMOS transistor and a second NMOS transistor, and the acquisition tube comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor. In the SRAM unit provided by the invention, the four transistors forming the first phase inverter and the second phase inverter all adopt L-shaped gates, and heavy doping body contact regions are arranged on outside regions of bending angles of the L-shaped gates. By the SRAM unit, power consumption leakage caused by a floating body effect in a PD SOI device and a parasitic triode effect and the threshold voltage drift of the transistor can be effectively prevented on the condition of sacrificing relatively small unit area, and the noise resistant ability of the unit is improved; according to the fabrication process, an extra mask is not introduced, and the fabrication process is completely compatible with a conventional logic process; and the interior of the unit adopts a central symmetrical structure, the matching of the size, the threshold voltage and the like of the MOS transistors are promoted, an array is further favorably formed, and a fully-customized SRAM chip is convenient.

Description

technical field [0001] The invention belongs to the field of memory design and production, and relates to an SOI dual-port SRAM unit and a production method thereof. Background technique [0002] Since the invention of SOI technology in the 1980s, it has small parasitic capacitance, low power consumption, fast speed and natural anti-Single-Event-Latchup (SEL) ability compared with ordinary bulk silicon technology, making SOI The technology is very suitable for working in System-on-Chips (SoC), low power consumption and radiation resistance; in addition, Static Random Access Memory (SRAM) is widely used in consumer electronics, automotive electronics, processor level Cache and L2 cache; therefore, applying SOI technology to SRAM design has certain advantages. [0003] According to the degree of depletion of the MOS tube body region, SOI can be further divided into fully depleted (Full-Depleted, FD) SOI and partially depleted (Partially-Depleted, FD) SOI. For partially deple...

Claims

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Application Information

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IPC IPC(8): H01L27/11H01L21/8244G11C11/413
CPCG11C11/413H10B10/12
Inventor 陈静何伟伟伍青青罗杰馨王曦
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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