Layer stripping method in chip failure analysis process

Abstract

The invention relates to a layer stripping method in a chip failure analysis process, comprising the following steps: (1) providing a chip, the chip has a multi-layer structure, and includes at least one target analysis layer, and the target analysis layer includes a layer to be analyzed area; (2) using ion beams to carry out peeling treatment from the surface of the chip, remove one or more layers above the target analysis layer, and expose the area to be analyzed, wherein the ion The beam includes at least one broad ion beam with a beam spot diameter not less than 1 mm. In this peeling method, the ion beam formed by at least one wide-beam ion beam can be used to obtain a relatively uniform peeling surface, which avoids a single beam of high-energy focused ion beam directly hitting the surface of the chip, causing damage to the target analysis area. The precision of peeling is effectively improved, and the processing range is expanded at the same time, and the peeling efficiency is high.

Description

technical field [0001] The invention relates to integrated circuit failure analysis, in particular to a layer stripping method in the chip failure analysis process. Background technique [0002] With the rapid development of semiconductor technology, the scale of integrated circuits is getting larger and larger, and integrated circuits are developing in the direction of multi-layer interconnection structures. The failure of integrated circuit chips often occurs in the interlayer metallization or active area of ​​the lower layer of the multilayer structure. The failure analysis of the chip must solve the observability of the lower layer of the multilayer structure, which requires the chip to be stripped. Under a high-magnification microscope, the specific layers of the chip are further observed and analyzed. [0003] The peeling treatment mainly includes: removing the passivation layer, removing the metallization layer, removing the interlayer oxide layer, etc. For differen...

AI Technical Summary

Problems solved by technology

However, focusing ion beams usually requires the use of Ga + source as the ion source, Ga + The source cost is high and the service life is short, which limits the application of focused ion beam stripping; more importantly, the beam spot size of focused ion beam is nm level, and the surface of the chip is bombarded with too concentrated high energy, so the stripping accuracy is difficult. Control, easy to cause damage to the target analysis area, making it difficult to continue the subsequent analysis work, and the area that can be processed by the nm-level beam spot is very limited, which limits the improvement of the efficiency of failure analysis

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