Gallium arsenide semiconductor substrate wet etching process

A wet etching, semiconductor technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of reduced performance reliability of semiconductor devices, defects in the perforation etching process, chemical residues, etc., and achieve higher prices. Competitiveness, shortening the processing process, the effect of expanding the production capacity

Active Publication Date: 2016-07-13
SUZHOU LIANG DONGXIN MICROELECTRONICS CO LTD
View PDF4 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Although the traditional chemical mechanical polishing process can remove the damaged crystal processing surface caused by the mechanical thinning process of the semiconductor substrate and release the stress generated, it has the following disadvantages: (1) It is inevitable that it will be difficult to clean after processing The chemical substances left on the surface of the substrate are very likely to cause defects in the subsequent backside perforation etching process, which will greatly reduce the performance reliability of the processed semiconductor device in the final client application; (2) Therefore, it must be targeted Design and add an additional effective surface cleaning follow-up process to thoroughly clean the chemical residues on the back surface of the semiconductor substrate; (3) It is necessary to purchase professional large-scale chemical mechanical polishing equipment and long-term purchase of special polishing pads and special chemicals. In addition, for III - V-group semiconductors also need to be equipped with complex chemical waste treatment systems to meet environmental protection requirements; (4) The cost of maintenance and use is very high

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0021] (1) Adhere the gallium arsenide semiconductor substrate that has been processed by the front-end device process on the sapphire carrier. The specific steps are: evenly coat the front surface of the gallium arsenide semiconductor substrate that has completed the front-end device process. Layer and adhesion layer, after curing the isolation layer and thin film layer at 80°C, the gallium arsenide semiconductor substrate and the sapphire carrier are adhered together by a hot press, and the overall thickness of the isolation layer and the adhesion layer is controlled at 10 μm.

[0022] (2) The gallium arsenide semiconductor substrate in step (1) is mechanically thinned using a DISCO grinder, the mechanical thinning is divided into coarse grinding and fine grinding, and the thinning thickness is 100 μm.

[0023] (3) The gallium arsenide semiconductor substrate in step (2) is immersed in an etching solution for chemical etching, and the etching solution is composed of NH 4 OH...

Embodiment 2

[0026] (1) Adhere the gallium arsenide semiconductor substrate that has been processed by the front-end device process on the sapphire carrier. The specific steps are: evenly coat the front surface of the gallium arsenide semiconductor substrate that has completed the front-end device process. Layer and adhesion layer, after curing the isolation layer and film layer at 85°C, the gallium arsenide semiconductor substrate and the sapphire carrier are adhered together by a hot press, and the overall thickness of the isolation layer and the adhesion layer is controlled at 20 μm.

[0027] (2) The gallium arsenide semiconductor substrate in step (1) is mechanically thinned using a DISCO grinder, the mechanical thinning is divided into coarse grinding and fine grinding, and the thickness of the thinning is 110 μm.

[0028] (3) The gallium arsenide semiconductor substrate in step (2) is immersed in an etching solution for chemical etching, and the etching solution is composed of NH 4 ...

Embodiment 3

[0031] (1) Adhere the gallium arsenide semiconductor substrate that has been processed by the front-end device process on the sapphire carrier. The specific steps are: evenly coat the front surface of the gallium arsenide semiconductor substrate that has completed the front-end device process. Layer and adhesion layer, after curing the isolation layer and film layer at 90°C, the gallium arsenide semiconductor substrate and the sapphire carrier are adhered together by a hot press, and the overall thickness of the isolation layer and the adhesion layer is controlled at 30 μm.

[0032] (2) The gallium arsenide semiconductor substrate in step (1) is mechanically thinned using a DISCO grinder, the mechanical thinning is divided into coarse grinding and fine grinding, and the thinning thickness is 120 μm.

[0033] (3) The gallium arsenide semiconductor substrate in step (2) is immersed in an etching solution for chemical etching, and the etching solution is composed of NH 4 OH, H ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
surface roughnessaaaaaaaaaa
Login to view more

Abstract

The invention discloses a gallium arsenide semiconductor substrate wet etching process comprising the following step of: (1) pasting a gallium arsenide semiconductor substrate having subjected to previous processing on a sapphire carrier; (2) mechanically thinning the gallium arsenide semiconductor substrate in the step (1); immersing the gallium arsenide semiconductor substrate in the step (2) in etching liquid to be subjected to chemical corrosion; (4) taking out, cleaning, and drying the chemically corroded gallium arsenide semiconductor substrate and directly performing later photoetching and subsequent processing on the gallium arsenide semiconductor substrate. The gallium arsenide semiconductor substrate wet etching process is simple in steps, good in operability, low in processing cost, may remove damaged crystal processing surface and releasing internal stress, does not need to purchase professional processing equipment and install a matching chemical waste processing system, greatly shortens later processing technological processes, benefits an increase in production power, reduces production cost, and enhances product price competitiveness.

Description

technical field [0001] The invention relates to the technical field of semiconductor processing, in particular to a gallium arsenide semiconductor substrate wet etching process. Background technique [0002] Semiconductors including Group III-V gallium arsenide substrates must undergo mechanical thinning on the back and subsequent back processing after the completion of the front-end device processing to make final usable semiconductor electronic devices, and the mechanical thinning process on the back of the semiconductor substrate takes The biggest problem is that it destroys the crystal structure of the semiconductor surface layer and causes internal stress in the substrate. Therefore, the follow-up process must be designed to remove the damaged crystal processing surface caused by the mechanical thinning process of the semiconductor substrate and release the stress generated. The follow-up traditional process method used on a large scale in the semiconductor industry is ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02
CPCH01L21/02016
Inventor 任华汪耀祖
Owner SUZHOU LIANG DONGXIN MICROELECTRONICS CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products