A Calculation Method for Minimum Storage Depth of Organic Field Effect Transistor Memory
A technology of storage depth and calculation method, applied in the direction of single semiconductor device testing, instruments, measuring devices, etc., to achieve the effect of good visualization, high calculation precision, and improved cognition
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Embodiment 1
[0034] A calculation method for the minimum storage depth of an electret type organic field effect transistor memory, comprising:
[0035] (1), prepare electret type organic field effect transistor memory, its thickness is d 1 , the dielectric constant see k 1 =3.0, the schematic diagram of its structure is as follows figure 1 shown;
[0036] It specifically includes the following steps: during actual preparation, the room temperature in the laboratory is kept at about 25° C., and the indoor humidity is kept below 30%.
[0037] (a) Polymer polyvinylcarbazole (PVK) solution is configured, and PVK is formulated into a solution with 1'2-dichloroethane (DCE) as a solvent, with a solubility of 10 mg / ml;
[0038] (b) select surface d 2 = 300nm silicon dioxide heavily doped silicon as substrate and gate insulating layer, k 2 =3.9, using acetone, ethanol, and deionized water to ultrasonically clean at 80KHZ for 10 minutes, then dry in a vacuum oven at 120°C;
[0039] (c) putting...
Embodiment 2
[0049] A calculation method for the minimum storage depth of an electret type organic field effect transistor memory, comprising:
[0050] (1), prepare electret type organic field effect transistor memory, its thickness is d 1 , the dielectric constant see k 1 =3.0, the schematic diagram of its structure is as follows figure 1 shown;
[0051] It specifically includes the following steps: during actual preparation, the room temperature in the laboratory is kept at about 25° C., and the indoor humidity is kept below 30%.
[0052] (a) Prepare a polymer poly(9,9-dioctylfluorenoxenthiadiazole) (F8BT) solution, and prepare F8BT with toluene as a solvent to form a solution with a solubility of 10 mg / ml;
[0053] (b) select surface d 2 = 300nm silicon dioxide heavily doped silicon as substrate and gate insulating layer, k 2 =3.9, using acetone, ethanol, and deionized water to ultrasonically clean at 80KHZ for 10 minutes, then dry in a vacuum oven at 120°C;
[0054] (c) putting t...
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