Formation method of semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure. The method comprises a step of providing a substrate with a bottom metal layer, a step of forming a dielectric layer which covers the surface of the substrate and the surface of the bottom metal layer, a step of forming a pattern layer at the surface of the dielectric layer, wherein the pattern layer has an opening inside, a step of etching the dielectric layer along the opening with the pattern layer as a mask until the surface of the bottom layer is exposed, forming a contact hole with a fluorine-containing polymer impurity in the dielectric layer, a step of removing the pattern layer, a step of using a hydrogen plasma to carry out first etching processing on the contact hole, and removing the fluoride ion in the fluorine-containing polymer impurity, a step of carrying out wet cleaning processing on the contact hole after the first etching processing, and a step of forming a conductive layer which fills the contact hole. According to the method, the damage of the dielectric layer and the bottom layer metal layer by the fluorine ion in Q-time is avoided, the production yield of the semiconductor structure is improved, and the chip output amount is raised.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the development of integrated circuits to ultra-large scale integrated circuits, the circuit density inside integrated circuits is increasing, and the number of components contained is also increasing. In a semiconductor integrated circuit, a Metal Oxide Semiconductor (MOS, Metal Oxide Semiconductor) transistor is one of the most important components. [0003] The existing MOS transistor process is to form a gate structure on a semiconductor substrate, and form a source region and a drain region in the semiconductor substrate on opposite sides of the gate structure; then form contacts on the gate structure, source region and drain region Hole (Contactvia), the contact hole is filled with metal to form a metal plug. However, the conduction performance between the metal ...

AI Technical Summary

Problems solved by technology

However, the conduction performance between the metal plug and the gate structure, the source region and the drain region needs to be improved and the contact resistance is relatively large. In order to improve the contact resistance between the metal plug and the gate structure, the source region and the drain region, usually Form metal silicide (Silicide), such as nickel silicide, on the surface of the source region, drain region and gate structure to reduce the contact resistance between the metal plug and the gate structure, source region and drain region

[0004] However, the yield rate and chip output of the prior art semiconductor structures still need to be improved

Images