Trench-gate power MOSFET and manufacturing method

Abstract

The invention discloses a trench-gate power MOSFET. The thicknesses of first gate dielectric layers in trenches in an internal region and second gate dielectric layers in the trenches in an edge region are independently set; and the thicknesses of the second gate dielectric layers are greater than those of the first gate dielectric layers. A threshold voltage of a device is adjusted through the thicknesses of the first gate dielectric layers; the electric field strength in the edge region is reduced and the voltage-withstand capability of the edge region is improved by increasing the thicknesses of the second gate dielectric layers; breakdown of the device is demanded in the internal region; and the impact resistance of the device is improved. The invention further discloses a manufacturing method of the trench-gate power MOSFET. The breakdown voltage of the device can be improved; and the anti-UIS impact ability of the device is improved. Independent adjustment of the thicknesses of the first gate dielectric layers and the second gate dielectric layers is achieved by source injection lithography; and an extra lithography process is not needed, so that the process cost is not increased.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a trench gate power MOSFET. The invention also relates to a method for manufacturing the trench gate power MOSFET. Background technique [0002] like Figure 1A Shown is a schematic diagram of the structure of the edge region of the existing trench gate power MOSFET; as Figure 1B Shown is a schematic diagram of the structure of the internal region of the existing trench gate power MOSFET; the device structure includes: [0003] A semiconductor substrate such as a silicon substrate 101 is formed on an epitaxial layer 102 on the surface of the semiconductor substrate 101 , and the drift region is composed of the epitaxial layer 102 . [0004] The groove of the trench gate is formed in the epitaxial layer 102, wherein the grooves in the inner region are marked with a mark 201, and there is a wider groove 202 in the edge region, that is, the width of ...

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Problems solved by technology

However, in the existing structure, because the depth of the trench 202 is deep, the devices are edge breakdown, and the poor uniformity of the distribution of the current path after the edge breakdown is likely to lead to the opening of the parasitic NPN transistor, thereby reducing the anti-abnormality of the device. Unclamped Inductive Switching (UIS) impact capability, UIS impact resistance is the ability of the device to load energy under avalanche breakdown

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