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46results about How to "No increase in process cost" patented technology

Shield gate trench power device and manufacturing method thereof

The invention discloses a shield gate trench power device. A gate structure of a device unit region comprises a shielding dielectric layer formed on the inner side surface of a gate trench; the shielding dielectric layer is formed by superposing a thermal oxidation layer and a CVD dielectric layer; active polycrystalline silicon is filled in a gap region formed by filling the shielding dielectriclayer; top trenches formed by etching part of the shielding dielectric layer close to the side surface of the gate trench are formed in two sides of the source polysilicon, and the top trenches are completely located in the thermal oxide layer; the shielding dielectric layer between the second side surface of the top trench and the source polysilicon is used as an inter-polysilicon dielectric layer; the top trench is filled with a polysilicon gate, and a gate dielectric layer is formed on the first side surface of the top trench. The invention further discloses a manufacturing method of the shield gate trench power device. According to the invention, the thickness uniformity of the side wall and the bottom shielding dielectric layer of the trench can be improved, so the voltage resistanceof the device can be ensured, the on resistance of the device can be reduced, and the gate-source capacitance of the device can be reduced.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

Semiconductor memory unit, driving method thereof and semiconductor memory

The invention relates to a semiconductor memory unit, a driving method thereof and a semiconductor memory, wherein the semiconductor memory unit comprises silicon on an insulator, a first diffusion region, a second diffusion region, a grid dielectric layer, a grid electrode, a first electric charge storage region and / or a second electric charge storage region, wherein the first diffusion region and the second diffusion region are positioned in top-layer silicon and mutually separated, and the conduction types of the first diffusion region and the second diffusion region are the same; the grid dielectric layer and the grid electrode are sequentially positioned on the top-layer silicon above a channel region; and the first electric charge storage region and / or the second electric charge storage region are / is respectively positioned in the grid dielectric layer and close to the part between the channel region and the first diffusion region and in the grid dielectric layer and close to the part between the channel region and the second diffusion region, and the first electric charge storage region and / or the second electric charge storage region are / is formed through electric field force. In the invention, the first electric charge storage region and / or the second electric charge storage region are / is formed in the grid dielectric layer through the electric field force to form the memory unit, and the memory unit is compatible with a traditional logic circuit forming process, thereby improving the performance of an integrated circuit and reducing the power consumption.
Owner:SEMICON MFG INT (SHANGHAI) CORP +1

Split-gate type memory and manufacturing method thereof

The invention provides a split-gate type memory and a manufacturing method thereof. According to the manufacturing method of the split-gate type memory, provided by the invention, the method comprises: a photoetching step for defining a shallow trench isolated region; a step for etching the shallow trench isolated region, wherein the height of the shallow trench isolated region of a word line region of a unit array in the split-gate type memory is reduced; a barrier layer removing step for removing the barrier layers of the regions not covered by photoresistance; a floating gate (FG) polysilicon etching step for etching floating gate polysilicon not covered by the photoresistance; and an FG and word line etching step for etching an FG and a word line. The height of the top end of the FG of the split-gate type memory manufactured according to the manufacturing method of the split-gate type memory, provided by the invention, is lowered, the capacitance between the FG and the word line is reduced, and the capacitance between the FG and a select line is maintained invariable, therefore, the capacitance coupling efficiency is accordingly reduced so as to be helpful to improving programming efficiency and reducing an erasing voltage.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

Method for manufacturing split-gate memory and split-gate memory

The invention provides a split-gate type memory and a manufacturing method thereof. According to the manufacturing method of the split-gate type memory, provided by the invention, the method comprises: a photoetching step for defining a shallow trench isolated region; a step for etching the shallow trench isolated region, wherein the height of the shallow trench isolated region of a word line region of a unit array in the split-gate type memory is reduced; a barrier layer removing step for removing the barrier layers of the regions not covered by photoresistance; a floating gate (FG) polysilicon etching step for etching floating gate polysilicon not covered by the photoresistance; and an FG and word line etching step for etching an FG and a word line. The height of the top end of the FG of the split-gate type memory manufactured according to the manufacturing method of the split-gate type memory, provided by the invention, is lowered, the capacitance between the FG and the word line is reduced, and the capacitance between the FG and a select line is maintained invariable, therefore, the capacitance coupling efficiency is accordingly reduced so as to be helpful to improving programming efficiency and reducing an erasing voltage.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

Integrated circuit protection structure and manufacturing method thereof

The invention provides an integrated circuit protection structure and a manufacturing method thereof. The integrated circuit protection structure comprises at least one ring of annular structure, wherein the annular structure comprises a first interconnection layer, a through hole layer and a second interconnection layer, wherein the first interconnection layer comprises at least one conductive part; the through hole layer comprises at least one conductive through hole, wherein the conductive through hole is connected to the upper portion of the conductive part, and the center of the conductive through hole deviates from the center of the conductive part; and the second interconnection layer comprises at least one conductive wire, wherein the conductive wire is connected above the conductive through hole. The asymmetric design is adopted for the axial symmetric design, wherein the center of the conductive through hole is deviated from the center of the lower-layer conductive part through transverse displacement, so that the conductive through hole completely or partially avoids the part of a hole of the lower conductive part, the conductive through hole can be effectively filled, the high-quality and reliable functions of a sealing ring, a protection ring and the like are facilitated, and influence to the later process is avoided. In addition, by adopting the scheme of the invention, the additional process cost is not increased.
Owner:YANGTZE MEMORY TECH CO LTD

Semiconductor memory unit, driving method thereof and semiconductor memory

The invention relates to a semiconductor memory unit, a driving method thereof and a semiconductor memory, wherein the semiconductor memory unit comprises silicon on an insulator, a first diffusion region, a second diffusion region, a grid dielectric layer, a grid electrode, a first electric charge storage region and / or a second electric charge storage region, wherein the first diffusion region and the second diffusion region are positioned in top-layer silicon and mutually separated, and the conduction types of the first diffusion region and the second diffusion region are the same; the griddielectric layer and the grid electrode are sequentially positioned on the top-layer silicon above a channel region; and the first electric charge storage region and / or the second electric charge storage region are / is respectively positioned in the grid dielectric layer and close to the part between the channel region and the first diffusion region and in the grid dielectric layer and close to the part between the channel region and the second diffusion region, and the first electric charge storage region and / or the second electric charge storage region are / is formed through electric field force. In the invention, the first electric charge storage region and / or the second electric charge storage region are / is formed in the grid dielectric layer through the electric field force to form thememory unit, and the memory unit is compatible with a traditional logic circuit forming process, thereby improving the performance of an integrated circuit and reducing the power consumption.
Owner:SEMICON MFG INT (SHANGHAI) CORP +1

High electron mobility transistor with coupling field plates

ActiveCN108847422AStrong lateral pressure resistanceUniform distribution of transverse electric fieldSemiconductor/solid-state device manufacturingSemiconductor devicesCouplingOptoelectronics
The present invention provides a high electron mobility transistor with coupling field plates. The transistor comprises a substrate. A buffer layer is arranged on the substrate, a channel layer is arranged on the buffer layer, a source electrode, a drain electrode and a barrier layer is arranged on the channel layer, the source electrode and the drain electrode are located on both ends of the barrier layer, and the barrier layer is located between the source electrode and the drain electrode. A dielectric layer and a gate electrode are arranged on the barrier layer. The surface of dielectric layer, between the gate electrode and the drain electrode, is provided with a plurality of coupling field plates, a coupling electrode is arranged on each coupling field plate, and each coupling electrode is connected with the source electrode via the corresponding metal interconnecting wire. According to the transistor, the coupling potential of each coupling field plates is changed via the size design of the corresponding coupling electrode and the corresponding coupling field plate, so that the regulating effect of coupling field plates on transverse electric field(s) is changed, the transverse electric field distribution of device(s) is optimized, and the transverse voltage endurance capability of the device(s) is improved.
Owner:济南半一电子有限公司

Dyeing process taking active emerald blue as main material

PendingCN112030576AQuality improvementReduce the color flowerDyeing processMedicineEngineering
The invention relates to a dyeing process taking active emerald blue as a main material. The dyeing process comprises the following steps that 1) to-be-dyed cloth is added into a dyeing machine, the to-be-dyed cloth is enabled to be soaked in water, and then the dyeing machine is operated; 2) dye and anhydrous sodium sulphate are separately added into the dyeing machine; and 3) alkali is added into the dyeing machine; wherein the steps satisfy the following conditions that (1) the dye comprises the active emerald blue; (2) a bath ratio of the to-be-dyed cloth to dye liquor is 1:(6 to 8), wherein the dye liquor is composed of the dye and the water, a weight of the dye is equal to or more than 1% of a weight of the to-be-dyed cloth, a dosage of the anhydrous sodium sulphate is 30 g/L to 70 g/L, and a dosage of the alkali is 15 g/L to 20 g/L; (3) after the anhydrous sodium sulphate is added, the anhydrous sodium sulphate can be uniformly distributed on the to-be-dyed cloth and in the water; and (4) after the alkali is added, the dye can be fixed on the to-be-dyed cloth. According to the process, other auxiliaries do not need to be added, dyeing defects can be effectively reduced onlyby adjusting the adding sequence and proportion of the dye, the anhydrous sodium sulphate and the alkali, the process complexity and the cost cannot be increased, even the process can be simplified, the cloth cover quality can be improved, and the dyeing effect is stable and reliable.
Owner:通亿(泉州)轻工有限公司

A method for obtaining ultra-fine pearlite of low-carbon and low-alloy black skin forged steel shaft

The invention relates to a method for obtaining a low-carbon low-alloy black skin forged-steel shaft superfine pearlite. The method comprises the steps that a decarburized layer on the surface of a low-carbon low-alloy black skin forged-steel shaft is utilized as a protective layer, the high-temperature black skin forged-steel shaft and cooling liquid perform transient heat exchange, the cooling speed is reduced through the protective layer, and accordingly a superfine pearlite structure is obtained. The method comprises the following steps that (a) the black skin forged-steel shaft is put in a heat treatment furnace and is heated to reach 30-50 DEG C above critical temperature, and heat preservation is performed for set time; (b) the shaft is discharged out of the furnace and precooled, wherein precooling is performed for set time; (c) the high-temperature black skin forged-steel shaft is put in the cooling liquid for transient cooling, and accordingly the superfine pearlite structure is obtained. By adopting the obtained superfine pearlite structure, the low-carbon low-alloy black skin forged-steel shaft can have good mechanical property, and especially the yield strength can be improved by 25-35% while the process cost is not increased.
Owner:ZHONGJUXIN OCEAN ENG EQUIP CO LTD
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