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34results about How to "Will not increase the difficulty of the process" patented technology

Film bulk acoustic wave resonator and preparation method thereof

InactiveCN101465628AHigh application frequencyReduce the requirements of the manufacturing process for equipmentImpedence networksThin-film bulk acoustic resonatorBulk acoustic wave
The invention discloses a thin film bulk acoustic wave resonator which comprises a substrate, a buffer layer, a piezoelectric layer and electrodes, and is characterized in that 1. A smooth concave groove and the buffer layer are arranged on the upper end surface of the substrate; the buffer layer crosses the concave groove and forms an air gap provided with a smooth upper convex edge with the substrate, and completely covers the air gap; the height of the lower top surface of the air gap is less than that of the substrate, and the air gap has flat surface and even change edge; 2. The edge of the buffer layer, which is contacted with the air gap and is close to the substrate is in smooth and outer-convex shape; the piezoelectric layer is arranged on the buffer layer; the electrodes include a bottom electrode and a top electrode; the bottom electrode is arranged in the piezoelectric layer on the buffer layer; the top electrode is arranged on the piezoelectric layer. The thin film bulk acoustic wave resonator has ingenious structure; a FBAR with stable structure and low loss can be fabricated on the substrate through the method, and the CMP process is avoided, so the thin film bulk acoustic wave resonator can be integrated into a CMOS chip conveniently.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

Display panel and display device

The invention discloses a display panel and a display device. The display panel comprises a first substrate, a binding area and a fan-out wiring area; the first substrate comprises a display area and a non-display area around the display area, and the display area comprises a plurality of signal leads; the binding area comprises a first conductive gasket group and a second conductive gasket group; the first conductive gasket group comprises a plurality of first conductive gaskets, and the second conductive gasket group comprises a plurality of second conductive gaskets; the fan-out wiring area comprises a plurality of first fan-out wires and a plurality of second fan-out wires; partial signal leads are electrically connected with the first conductive gaskets through the first fan-out wires, and partial signal leads are electrically connected with the second conductive gaskets through the second fan-out wires; each second fan-out wiring comprises a first wire segment and a second wire segment connected with the first wire segment, and the first wire segments and the second wire segments are located on different film layers; at least partial overlapping areas exist between the orthographic projections of the second conductive gaskets and the orthographic projections of the first wire segments which are correspondingly and electrically connected with the second conductive gaskets, wherein the orthographic projections are all on the plane where the first substrate is located. Thus, the implementation of narrow bezel design is facilitated.
Owner:XIAMEN TIANMA MICRO ELECTRONICS

Metal oxide thin film transistor and preparation method thereof

The invention discloses a metal oxide thin film transistor and a preparation method thereof. The metal oxide thin film transistor is composed of a grid electrode, an insulating layer, a transition layer, a semiconductor layer, a drain electrode and a source electrode, wherein the grid electrode, the insulating layer, the transition layer and the semiconductor layer are sequentially connected with each other from bottom to top; the drain electrode and the source electrode are positioned on the semiconductor layer; the transition layer and the semiconductor layer are prepared by means of sputtering with the same target being adopted in the process of sputtering, the material of the target is (In2O3)x(Ga2O3)y(ZnO)z, wherein x, y and z are not less than 0 but not more than 1, and x+y+z is equal to 1; and the transition layer and the insulating layer include excellent contact property so as to effectively lower carrier trap density between contact interfaces of the insulating layer and the transition layer as well as enhance output current of the transistor and improve electrical stability. The source electrode and the drain electrode can form outstanding ohmic contact with the semiconductor layer, thereby effectively reducing off-state current, raising on/off ratio of current and improving electronic carrier mobility.
Owner:SOUTH CHINA UNIV OF TECH

PMOS (p-channel metal-oxide-semiconductor field-effect transistor) source/drain region ion implantation method and corresponding device manufacturing method

The invention discloses a PMOS (p-channel metal-oxide-semiconductor field-effect transistor) source / drain region ion implantation method and a corresponding device manufacturing method. Since an amorphous carbon layer can be completely removed without causing silicon sinking, when the amorphous carbon layer is used as a pad layer for PMOS source / drain region ion implantation, the range of implanted impurities in the silicon substrate can be reduced on the premise of basically not changing the implanted impurity distribution, thereby obtaining an ultrashallow junction which is more shallow than that obtained by a conventional method; or the implanted energy is increased on the premise of keeping the depth of the ultrashallow junction unchanged, thereby relieving the demands of technique for high-dose low-energy ion implantation to some extent, and lowering the technical difficulty of PMOS source / drain region ion implantation. The PMOS source / drain region ion implantation method and the corresponding device manufacturing method provided by the invention can be used for improving the ion implantation technique of the ultrashallow junction in the PMOS source / drain region, and lowering the technical difficulty.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP

Metal gallium oxide doping transparent conductive membrane used for ultraviolet waveband and preparation method thereof

The invention discloses a metal gallium oxide doping transparent conductive membrane used for ultraviolet waveband and a preparation method thereof. The method comprises the steps that a layer of contact layer membrane firstly grows on a substrate, and annealing is conducted at the nitrogen-oxygen atmosphere of 400 DEG C-600 DEG C by a rapid thermal annealing furnace after the contact layer membrane grows; a first Ga2O3 membrane layer grows through sputtering under the condition of magnetic controlled argon sputtering; a doped membrane grows through sputtering under the condition of magnetic controlled argon sputtering; a second Ga2O3 membrane layer grows through sputtering under the condition of magnetic controlled argon sputtering, and annealing is conducted on completely growing membranes integrally at the nitrogen-oxygen atmosphere of 500 DEG C-600 DEG C by the rapid thermal annealing furnace, and membrane materials mutually penetrate, disperse and melt to form the metal doped Ga2O3 membrane. The transparent conductive membrane has higher membrane optical permeability and lower membrane square resistance on the basis of an ITO transparent conductive membrane.
Owner:ZHONGSHAN INST OF MODERN IND TECH SOUTH CHINA UNIV OF TECH +1

High-creep-resistance ultra-high molecular weight polyethylene fiber and preparation method thereof

The invention provides high-creep-resistance ultra-high molecular weight polyethylene fiber and a preparation method thereof. The preparation method comprises the following steps of S1, mixing ultra-high molecular weight polyethylene powder, a mixed solvent, an antioxidant and a sensitizer according to a preset proportion, and performing stirring to obtain a uniform mixed suspension; S2, putting the mixed suspension into a double-screw extruder for spinning treatment, then obtaining primary gel filament through a cooling water bath, extracting the primary gel filament through a mixed extraction solution containing the antioxidant, performing drying, and then obtaining a primary fiber product through multi-stage hot drafting and multi-stage drying in a drying oven; and S3, performing irradiation crosslinking: performing irradiation treatment of a predetermined dose on the primary fiber product, and finally performing annealing treatment under a nitrogen condition to obtain the high-creep-resistance ultra-high molecular weight polyethylene fiber. Compared with conventional ultra-high molecular weight polyethylene fiber, the creep elongation of the high-creep-resistance ultra-high molecular weight polyethylene fiber prepared by the invention is reduced by 50% or above.
Owner:WUHAN TEXTILE UNIV +2

Groove-type MOS device and manufacturing method thereof

The invention provides a groove-type MOS (Metal-Oxide-Semiconductor) device and a manufacturing method thereof. The groove-type MOS device at least includes a first conductive heavily doped substrate,a first conductive lightly doped epitaxial layer on the first conductive heavily doped substrate, a plurality of first conductive source regions, a plurality of grooves, a gate oxide layer and a polysilicon gate which are formed in the each groove, a second conductive lightly doped body region formed on the upper portion of the first conductive lightly doped epitaxial layer, a cellular region contact hole formed in the second conductive lightly doped body region, an insulating dielectric block covering the polysilicon gate in the groove of the cellular region, a second conductive heavily doped body contact region formed between two adjacent first conductive source regions of the cellular region, and a metal source electrode formed in the contact hole of the cellular region, wherein the plurality of first conductive source regions and the plurality of grooves are formed on the upper portion of the first conductive lightly doped epitaxial layer at intervals. The groove-type MOS device can guarantee stability of the device while improving the device density and reducing the conduction resistance.
Owner:CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD

System process method for fertilizer making through perishable garbage fermentation

The invention relates to the technical field of solid waste treatment, in particular to a system process method for fertilizer making through perishable garbage fermentation. The system process methodcomprises the steps: to-be-treated garbage is crushed and separated firstly, and refractory organic matter is removed; and then water is added to adjust the solid content of the garbage, slurry is prepared, and micron bubbles are introduced into the slurry. The refractory organic matter such as plastic and fabrics and imputrescible inorganic matter such as glass, ceramic, gravel and metal are removed to the greatest extent; the content of the heavy metal in garbage derived fertilizer can be effectively decreased and stably controlled, the uncertainty of the content of the heavy metal in the garbage derived fertilizer is eliminated, and convenience is provided for application of the garbage derived fertilizer; and the content of the organic matter and the content of the water in sinking and separated muddy sand materials with the large specific gravity are low, and the sinking and separated muddy sand materials with the large specific gravity meet the requirements of being subjected todirect landfill and used as raw materials of building materials.
Owner:中原环资科技有限公司

Transistor and transistor forming method

The invention relates to a transistor and a transistor forming method, wherein the transistor forming method comprises the following steps that a semiconductor substrate is provided; at least two grooves are formed in the semiconductor substrate; insulation layers filling the grooves are formed in the grooves, and in addition, the tops of the insulation layers are set to be lower than the surface of the semiconductor substrate; epitaxial layers are formed on the surface and the side wall of the semiconductor substrate higher than the tops of the isolation layers, and in addition, the epitaxial layers are enabled to cover the partial isolation layers arranged at the two sides of the semiconductor substrate; a well region is formed in the semiconductor substrate and the epitaxial layers; a gate electrode structure is formed on the surface of each epitaxial layer, wherein each gate electrode structure comprises a gate dielectric layer covering the surface of the corresponding epitaxial layer and a gate conducting layer positioned on the top of the grate dielectric layer; light doping regions are formed in the epitaxial layers arranged at the two sides of the grate conducting layers; a heavy doping region is formed in each light doping region, and in addition, the heavy doping regions and the well region are isolated by the light doping regions and the isolation layers. The transistor formed by the method provided by the invention has low power consumption, the operation speed is high, the groove dimension is small, and in addition, the warping effect can be effectively eliminated.
Owner:SEMICON MFG INT (SHANGHAI) CORP

A trench type MOS device and its manufacturing method

The invention provides a groove-type MOS (Metal-Oxide-Semiconductor) device and a manufacturing method thereof. The groove-type MOS device at least includes a first conductive heavily doped substrate,a first conductive lightly doped epitaxial layer on the first conductive heavily doped substrate, a plurality of first conductive source regions, a plurality of grooves, a gate oxide layer and a polysilicon gate which are formed in the each groove, a second conductive lightly doped body region formed on the upper portion of the first conductive lightly doped epitaxial layer, a cellular region contact hole formed in the second conductive lightly doped body region, an insulating dielectric block covering the polysilicon gate in the groove of the cellular region, a second conductive heavily doped body contact region formed between two adjacent first conductive source regions of the cellular region, and a metal source electrode formed in the contact hole of the cellular region, wherein the plurality of first conductive source regions and the plurality of grooves are formed on the upper portion of the first conductive lightly doped epitaxial layer at intervals. The groove-type MOS device can guarantee stability of the device while improving the device density and reducing the conduction resistance.
Owner:CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD

PMOS (p-channel metal-oxide-semiconductor field-effect transistor) source/drain region ion implantation method and corresponding device manufacturing method

The invention discloses a PMOS (p-channel metal-oxide-semiconductor field-effect transistor) source / drain region ion implantation method and a corresponding device manufacturing method. Since an amorphous carbon layer can be completely removed without causing silicon sinking, when the amorphous carbon layer is used as a pad layer for PMOS source / drain region ion implantation, the range of implanted impurities in the silicon substrate can be reduced on the premise of basically not changing the implanted impurity distribution, thereby obtaining an ultrashallow junction which is more shallow than that obtained by a conventional method; or the implanted energy is increased on the premise of keeping the depth of the ultrashallow junction unchanged, thereby relieving the demands of technique for high-dose low-energy ion implantation to some extent, and lowering the technical difficulty of PMOS source / drain region ion implantation. The PMOS source / drain region ion implantation method and the corresponding device manufacturing method provided by the invention can be used for improving the ion implantation technique of the ultrashallow junction in the PMOS source / drain region, and lowering the technical difficulty.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP

Display screen design method and device

The invention provides a display screen design method and device, and the method comprises the steps: determining a first grid line disposed between a first pixel and a second pixel in a target display screen, enabling the area of the first pixel to be larger than that of the second pixel, enabling the first pixel to be adjacent to the second pixel, and according to a first preset shielding view angle, determining a first interval between the first pixel and the first grid line, the first interval being smaller than a second interval between the second pixel and the first grid line, and then determining the position of the first grid line between the two pixels according to the first interval, i.e., adjusting the position of the first grid line, so that the grid line is close to the pixelwith a larger area, and the pixel with a larger area is obtained. The grid lines are separated from the pixels with smaller areas, so that the shielding of the grid lines to the pixels with differentsizes is approximately consistent, the color cast phenomenon of a large viewing angle is improved, the thickness of the packaging layer is not changed, the product performance is not reduced, the width of the grid lines is not changed, and the process difficulty is not increased.
Owner:HEFEI VISIONOX TECH CO LTD

Film bulk acoustic wave resonator and preparation method thereof

InactiveCN101465628BHigh application frequencyReduce the requirements of the manufacturing process for equipmentImpedence networksThin-film bulk acoustic resonatorBulk acoustic wave
The invention discloses a thin film bulk acoustic wave resonator which comprises a substrate, a buffer layer, a piezoelectric layer and electrodes, and is characterized in that 1. A smooth concave groove and the buffer layer are arranged on the upper end surface of the substrate; the buffer layer crosses the concave groove and forms an air gap provided with a smooth upper convex edge with the substrate, and completely covers the air gap; the height of the lower top surface of the air gap is less than that of the substrate, and the air gap has flat surface and even change edge; 2. The edge of the buffer layer, which is contacted with the air gap and is close to the substrate is in smooth and outer-convex shape; the piezoelectric layer is arranged on the buffer layer; the electrodes includea bottom electrode and a top electrode; the bottom electrode is arranged in the piezoelectric layer on the buffer layer; the top electrode is arranged on the piezoelectric layer. The thin film bulk acoustic wave resonator has ingenious structure; a FBAR with stable structure and low loss can be fabricated on the substrate through the method, and the CMP process is avoided, so the thin film bulk acoustic wave resonator can be integrated into a CMOS chip conveniently.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

A kind of high creep resistance ultra-high molecular weight polyethylene fiber and preparation method thereof

The invention provides a high creep-resistant ultra-high molecular weight polyethylene fiber and a preparation method thereof. The preparation method is as follows: S1, mixing ultra-high molecular weight polyethylene powder, mixed solvent, antioxidant and sensitizer in a predetermined proportion, and stirring to obtain a uniform mixed suspension; S2, placing the mixed suspension in a twin-screw extruder After spinning out of the machine, the primary jelly filaments are obtained through a cooling water bath; the nascent jelly filaments are extracted with a mixed extract containing antioxidants and then dried, and then subjected to multi-stage thermal drawing and multi-stage heat drawing. graded oven to obtain the initial fiber product; S3, radiation crosslinking: the initial fiber product is subjected to a predetermined dose of irradiation treatment, and finally annealed under nitrogen conditions to obtain high creep-resistant ultra-high molecular weight polyethylene fibers. Compared with conventional ultra-high molecular weight polyethylene fibers, the fiber creep elongation of the high-creep-resistant ultra-high molecular weight polyethylene fibers prepared by the present invention is reduced by 50% or more.
Owner:WUHAN TEXTILE UNIV +2

Transistor and method for forming the transistor

The invention relates to a transistor and a transistor forming method, wherein the transistor forming method comprises the following steps that a semiconductor substrate is provided; at least two grooves are formed in the semiconductor substrate; insulation layers filling the grooves are formed in the grooves, and in addition, the tops of the insulation layers are set to be lower than the surface of the semiconductor substrate; epitaxial layers are formed on the surface and the side wall of the semiconductor substrate higher than the tops of the isolation layers, and in addition, the epitaxial layers are enabled to cover the partial isolation layers arranged at the two sides of the semiconductor substrate; a well region is formed in the semiconductor substrate and the epitaxial layers; a gate electrode structure is formed on the surface of each epitaxial layer, wherein each gate electrode structure comprises a gate dielectric layer covering the surface of the corresponding epitaxial layer and a gate conducting layer positioned on the top of the grate dielectric layer; light doping regions are formed in the epitaxial layers arranged at the two sides of the grate conducting layers; a heavy doping region is formed in each light doping region, and in addition, the heavy doping regions and the well region are isolated by the light doping regions and the isolation layers. The transistor formed by the method provided by the invention has low power consumption, the operation speed is high, the groove dimension is small, and in addition, the warping effect can be effectively eliminated.
Owner:SEMICON MFG INT (SHANGHAI) CORP
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