TSV electroplating method and TSV electroplating system under action of ultrasonic outfield

Abstract

The invention discloses a TSV (Through Silicon Via) electroplating method and a TSV electroplating system under the action of ultrasonic outfield. The TSV electroplating method comprises the following steps that Step 1, a silicon wafer having TSV micro blind holes is put in a sealed container filled with an electroplating solution containing an additive, vacuumizing pretreatment is carried out on the sealed container to allow the electroplating solution to soak into the TSV micro blind holes, then standing for 10-60min is carried out till the additive reaches preliminary adsorption equilibrium in the inner surfaces of the TSV micro blind holes; Step 2, the silicon wafer is connected with a cathode of an electroplating power supply, and then is put in an electroplating bath to act as an electroplating cathode; and Step 3, the electroplating power supply is started for carrying out cathode copper ion deposition reaction, in the meanwhile, an ultrasonic power supply is started to apply ultrasonic excitation into the TSV micro blind holes, and by using the ultrasonic cavitation effect, inhibition to hole opening electroplating of the TSV micro blind holes and acceleration of hole bottom electroplating are realized, and bottom-up complete filling is formed. According to the TSV electroplating method and the TSV electroplating system, ultrasonic can be effectively used as an extra energy field to enhance TSV copper electroplating filling.

Description

technical field [0001] The invention relates to a new method for improving the electroplating effect of TSV micro-blind holes, which belongs to the field of semiconductor three-dimensional packaging. Background technique [0002] Integrated circuit technology develops rapidly with Moore's Law, and higher circuit integration density leads to higher interconnection density. Stacking and integrating chips with different functions (such as memory, processor, etc.) into a three-dimensional integrated package of a multifunctional system has become an inevitable choice to improve device performance and cost performance. [0003] A solution for three-dimensional integration adopts a large number of high-density TSVs (Through Silicon Via, through-silicon vias) that run through the silicon substrate to realize the vertical interconnection between stacked chips and form high-density three-dimensional integration, bringing "high density, Versatility, small size" many advantages. Among...

AI Technical Summary

Problems solved by technology

Makes the role of ultrasound-enhanced plating in TSV filling insignificant

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