Partial Silicon-on-Insulator (PSOI) thin film-LDMOS transistor with short drift region

Abstract

The invention discloses a Partial Silicon-on-Insulator (PSOI) thin film-LDMOS transistor with a short drift region, and belongs to the electronic components field; the transistor at least comprises the following elements: a substrate layer; an oxide layer with a silicon window on one side and a buried oxide layer on the other side; a thin film layer comprising a source zone, an integral silicon zone, a drift region, and a leakage zone; a top layer comprising a thin oxide layer, a thick oxide layer, a grid electrode, a source electrode and a drain electrode. The PSOI-thin film-LDMOS transistor is miniature, has the short drift region, is high in breakdown voltage, low in low conduction resistance, high in driving capability, and can be applied to an electronic circuit board.

Description

technical field [0001] The invention relates to a transistor, in particular to an LDMOS transistor. Background technique [0002] The development trend of semiconductor power integrated circuits can be divided into two directions, one is to develop in the direction of high voltage and high power characteristics, and the other is to develop in the direction of intelligence and miniaturization. Under the requirements of low power consumption and miniaturization of current communication systems and communication terminals, the core issue for power integrated circuits is how to further reduce the size of power devices under the premise of ensuring sufficient high back pressure and power, so as to be compatible with traditional Compatible with silicon integrated circuits and achieve process integration. [0003] For high-voltage characteristics and high-power performance, the performance of semiconductor power devices is mainly improved by improving device power control capacity...

AI Technical Summary

Problems solved by technology

However, the traditional PSOI structure LDMOS film layer is relatively thick, and the thickness is generally greater than 1 micron.

Moreover, in order to reduce the surface electric field and increase the breakdown voltage, the length of the drift region is generally greater than 15 microns or even 100 microns, resulting in poor RESURF (REduced SURface Field, RESURF) effect of LDMOS.

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