A kind of vertical channel SIC junction gate bipolar transistor and its preparation method
A bipolar transistor and junction gate technology, applied in the field of microelectronics, can solve the problems of complex structure, low production cost and yield, and prone to latch-up effect, so as to avoid the influence of device characteristics and reduce the difficulty of device process Effect
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Embodiment 1
[0046] A SiC junction gate bipolar transistor device with a vertical channel, specifically as figure 2 As shown, including an N+ silicon carbide substrate 2, an emitter contact metal layer 1 formed on the surface of the N+ silicon carbide substrate 2, a P+ buffer layer 3 formed on the N+ silicon carbide substrate 2, and a P+ buffer layer 3 formed on the P-drift region 4, P+ collector region 8 formed on P-drift region 4, collector contact metal layer 9 formed on P+ collector region 8; also includes at least two P+ collector regions formed on P-drift region 4 a vertical trench, the bottom of the trench and the side walls of the trench are provided with an N-type gate region 7, the N-type gate region 7 at the bottom of the trench is implanted with a gate N+ implantation region 5, and the gate N+ implantation region 5 is formed with a The gate is in contact with the metal layer 6 ; the N-type gate region 7 is in contact with the P+ collector region 8 .
[0047] Among them, the e...
Embodiment 2
[0075] A SiC junction gate bipolar transistor device with a vertical channel, specifically as figure 2 As shown, including an N+ silicon carbide substrate 2, an emitter contact metal layer 1 formed on the surface of the N+ silicon carbide substrate 2, a P+ buffer layer 3 formed on the N+ silicon carbide substrate 2, and a P+ buffer layer 3 formed on the P-drift region 4, P+ collector region 8 formed on P-drift region 4, collector contact metal layer 9 formed on P+ collector region 8; also includes at least two P+ collector regions formed on P-drift region 4 a vertical trench, the bottom of the trench and the side walls of the trench are provided with an N-type gate region 7, the N-type gate region 7 at the bottom of the trench is implanted with a gate N+ implantation region 5, and the gate N+ implantation region 5 is formed with a The gate is in contact with the metal layer 6 ; the N-type gate region 7 is in contact with the P+ collector region 8 .
[0076] Among them, the e...
Embodiment 3
[0104] A SiC junction gate bipolar transistor device with a vertical channel, specifically as figure 2 As shown, including an N+ silicon carbide substrate 2, an emitter contact metal layer 1 formed on the surface of the N+ silicon carbide substrate 2, a P+ buffer layer 3 formed on the N+ silicon carbide substrate 2, and a P+ buffer layer 3 formed on the P-drift region 4, P+ collector region 8 formed on P-drift region 4, collector contact metal layer 9 formed on P+ collector region 8; also includes at least two P+ collector regions formed on P-drift region 4 a vertical trench, the bottom of the trench and the side walls of the trench are provided with an N-type gate region 7, the N-type gate region 7 at the bottom of the trench is implanted with a gate N+ implantation region 5, and the gate N+ implantation region 5 is formed with a The gate is in contact with the metal layer 6 ; the N-type gate region 7 is in contact with the P+ collector region 8 .
[0105] Among them, the e...
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