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Parallel implementation method of real-time phase noise hardware generators

A technology of phase noise and implementation method, applied in digital function generators, instruments, digital data processing components, etc., can solve problems such as low speed and poor real-time performance, and achieve the effect of large bandwidth, good quality, and low FPGA resource consumption

Inactive Publication Date: 2017-05-31
BEIJING INSTITUTE OF TECHNOLOGYGY +1
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Problems solved by technology

However, the existing methods based on time-domain filtering have poor real-time performance and low speed when realizing phase noise simulation.

Method used

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  • Parallel implementation method of real-time phase noise hardware generators
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  • Parallel implementation method of real-time phase noise hardware generators

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Embodiment Construction

[0034] The present invention will be described in detail below with reference to the accompanying drawings and examples.

[0035]The invention provides a parallel implementation method of a real-time phase noise hardware generator. According to the cellular automata theory and the IIR filtering process, power-law spectral noise is generated in parallel, real-time and high-speed on the FPGA, and on this basis and effectively Signal superposition to complete parameter controllable phase noise simulation. Firstly, according to the noise cycle length, the high-speed sampling frequency of the actual system and the FPGA low-speed working clock, etc., the order, rules and parallel paths of the cellular automata are determined; subsequently, according to the order and rules of the cellular automata, the Reed algorithm or look-up table to obtain regular vectors; at the same time, according to the theory of cellular automata, the N-way initial vectors and function recursion relations re...

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Abstract

The invention discloses a parallel implementation method of real-time phase noise hardware generators. By the adoption of the method, real-time, high-speed and parallel phase noise simulation can be achieved at an FPGA processor. According to the method, firstly, on the basis of the FPGA high-speed and parallel implementation method of uniform white noise of a cellular automaton theory, a calculation method of N-way initialization vectors needed by the parallel implementation and a recurrence function relation of the parallel generating algorithm of the cellular automaton are given; then, on the basis of real-time parallel generation of white noise, parallel first-order IIR filter banks are designed, and by setting a gain value at a corner frequency, noise output which meets features of a power law spectrum is achieved by filtering; finally, an equivalent form of the phase noise is obtained from the white noise, and is superposed with effective signals to complete the phase noise simulation. Under the condition of low FPGA source consumption, the method rapidly generates white noise which is long in cycle, large in band width and good in quality in real time, and on this basis, a parameter-controllable phase-noise simulation hardware generator is achieved.

Description

technical field [0001] The invention relates to the technical field of satellite communication system simulation and phase noise modeling, in particular to a parallel implementation method of a real-time phase noise hardware generator. Background technique [0002] Satellite communication system simulation technology can reproduce an ideal, degraded, or even near-real radio wave propagation environment on the ground, and simulate the influence of various time and space changes in the satellite communication link on signal propagation, and has long become a technology of communication, measurement and control, etc. Indispensable means of verification testing in the field. During the transmission process of satellite communication links, radio waves will inevitably be affected by random non-ideal characteristics such as noise interference, channel fading, ionospheric scintillation, and transponder nonlinearity. Among them, one of the main factors affecting the bit error rate ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/02
CPCG06F1/022
Inventor 郑哲黄惠明周扬单长胜吴嗣亮丁华王磊张晖
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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