SOI-LIGBT device capable of suppressing Snapback phenomenon and manufacturing method thereof
A technology of devices and phenomena, applied in the field of SOI-LIGBT devices and their manufacturing, can solve problems affecting device performance and achieve the effects of reducing device area, reducing device cost, and uniform distribution
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[0057] Example 1
[0058] Such as figure 2 As shown, figure 2 It is a schematic diagram of a SOI-LIGBT device that can suppress the Snapback phenomenon of this embodiment; its cell structure includes a substrate 1, a buried oxide layer on the upper surface of the substrate 1, a thick dielectric layer 3 above the buried oxide layer 2, and a thick The thick silicon drift region 4 on the left side of the dielectric layer 3, the P-well region 12 on the left end of the thick silicon drift region 4, the independent P-type heavily doped emitter regions 11 and the second P-type heavily doped emitter regions 11 and the second P-well region arranged in the P-well region 12 An N-type heavily doped region 42, an N-type buffer region 41 extending through the right end of the thick dielectric layer 3 in the longitudinal direction, a P-type heavily doped collector region 13 and an N-type buffer region 41 at the left end of the N-type buffer region 41 The second N-type heavily doped region 45 ...
Example Embodiment
[0074] Example 2
[0075] Such as image 3 As shown, this embodiment is basically the same as Embodiment 1, the difference is: the collector dielectric barrier layer 31 in this embodiment includes multiple sub-barrier layers separated by the N-type buffer region 41 in the Z direction, and adjacent sub-layers The distance between the barrier layers in the Z direction is a.
Example Embodiment
[0076] Example 3
[0077] Such as Figure 4 As shown, this embodiment is basically the same as Embodiment 1, with the difference that: in this embodiment, the N strips 44 and P strips 14 are not in contact with the upper surface of the buried oxide layer 2.
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