Trench gate SOI-LIGBT device structure with low turn-off loss
A technology of turn-off loss and device structure, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of very high process requirements and unsatisfactory turn-off loss effects, and achieve carrier recombination reduction, carrier Uniform distribution and reduced turn-off loss
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Embodiment 1
[0022] Such as figure 2 As shown, a low turn-off loss trench gate SOI-LIGBT device structure includes a P-type substrate 9, a buried oxide layer of silicon dioxide 8, an N-type drift region 3, and the inside of the N-type drift region 3. One end is provided with a P-type well region 4, the other end is provided with an N-buffer layer 2, an oxide layer 10 is provided on the surface of the device, and an N-type source terminal 5 and an N-type source terminal 5 are provided above the inside of the P-type well region 4. The adjacent P-type contact region 6; the N-type anode region 1 is arranged above the inside of the N-buffer layer 2; the metal layer is arranged above the N-type source terminal 5, the P-type contact region 6 and the N-type anode region 1 The right side of the channel between the source end 5 and the P-type well region 4 is a gate oxide layer, and the right side of the gate oxide layer is polysilicon 7, and the polysilicon 7 is located on the right side of the P-...
Embodiment 2
[0026] Such as image 3 As shown, the low turn-off loss slot gate SOI-LIGBT structure of this embodiment is basically the same as that of Embodiment 1, the difference is that the N-type drift region 3 between the P-type well region 4 and the N-buffer layer 2 is provided with Silicon dioxide tank dielectric 11 ; the silicon dioxide tank dielectric 11 is located on the right side of the polysilicon 7 .
[0027] The length of the silica trough dielectric 11 is Wt, which has a minimum value of 1 μm.
[0028] Preferably, the right side of the silicon dioxide tank medium 11 can be connected to the left side of the N-buffer layer 2, that is, L d to zero.
[0029] The depth of the silicon dioxide trench dielectric 11 is Dt, which is greater than the depth Lg of the polysilicon 7 and satisfies the thickness of the silicon layer, that is, the thickness of the N-type drift region 3 ts>Dt≥Lg+1um.
[0030] Compared with the conventional groove gate SOI-LIGBT device, the groove gate of t...
Embodiment 3
[0032] Such as Figure 7 As shown, the low turn-off loss slot-gate SOI-LIGBT structure of this embodiment is basically the same as that of Embodiment 2, except that an N-type carrier storage layer 12 is provided under the P-type well region 4 .
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