Array substrate and liquid crystal display panel
An array substrate and thin film transistor technology, applied in the field of liquid crystal display, can solve the problems of affecting production capacity and long detection time, and achieve the effect of ensuring uniformity
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Embodiment 1
[0030] image 3 is a partial structural schematic diagram of Embodiment 1 of the array substrate of the present invention; Figure 4 yes image 3 The cross-sectional view of the array substrate shown along the direction A-A; Figure 5 yes image 3The cross-sectional view of the array substrate shown along the B-B direction. see Figure 3 to Figure 5 , the array substrate 100 also includes a substrate glass 17, the LCQ test wiring 11, the driving wiring 12, the ADD wiring 13, the first thin film transistor 14, the second thin film transistor 15 And the third thin film transistor 16 is disposed on one side of the substrate glass 17 . The first thin film transistor 14, the second thin film transistor 15, and the third thin film transistor 16 all include a gate electrode 141, a gate insulating layer 142, a semiconductor layer 143, and a first electrode disposed on one side of the substrate glass 17. 144 and a second electrode 145, the gate insulating layer 142 is located bet...
Embodiment 2
[0037] Figure 6 It is a partial cross-sectional view of Embodiment 2 of the array substrate of the present invention. see Figure 6 , the array substrate 200 includes a plurality of LCQ test wirings, a plurality of driving wirings composed of gate lines gate and data lines data, ADD wirings, a plurality of first thin film transistors, a plurality of second thin film transistors, a plurality of The third thin film transistor, the pixel unit connected to the gate line gate and the data line data, the substrate glass 27 and the insulating protection layer 28, the first thin film transistor, the second thin film transistor and the third thin film transistor The thin film transistors all include a gate electrode 241, a gate insulating layer 242, a semiconductor layer 243, a first electrode 244, a second electrode 245, a first contact layer 249 and the second contact layer 250 arranged on one side of the substrate glass 27, The gate insulating layer 242 is located between the gat...
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