MEMS encapsulation structure with encapsulation spacing capable of being controlled in high precision and encapsulation method
A packaging structure and packaging method technology, applied in the manufacture of microstructure devices, microstructure devices, microstructure technology, etc., can solve the problem of uncontrollable packaging spacing, and achieve the effect of reducing manufacturing difficulty, realizing output, and improving output
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[0060] Preferably, the preparation method of the encapsulation limiting device includes the following steps: preparing a metal seed layer on the surface of the silicon wafer by etching or stripping; preparing a patterned photoresist mask on the seed layer by using photolithography alignment technology During electroplating, the photoresist mask is used as an inverted mold to limit the electroplating position; for electroplating, different electroplating times are used to control the thickness of electroplating in different functional areas, so as to realize three-dimensional electroplating; after electroplating is completed, the photoresist mask is removed ; According to actual needs, the etching method is used to remove the seed layer in some parts.
[0061] Preferably, the position of the limiting device should be near the packaging ring. The plating thickness of the limiting device can be prepared by selecting different plating times according to the needs of the device itse...
Embodiment 1
[0074] A MEMS packaging method with high-precision controllable packaging spacing provided by the present invention comprises the following steps:
[0075] (1) Prepare a scattered metal seed layer on the surface of the silicon substrate by etching or stripping. The position of the metal seed layer corresponds to the position of the limiting device, the first packaging ring and the first metal plate. The metal The seed layer is used to fix the limiting device, the first packaging ring and the first metal plate on the upper end of the silicon substrate.
[0076] For example, the metal seed layer 17 (Cr / Au) required for the device can be prepared on the silicon substrate 1 by deposition, etching or stripping processes, and the thickness of the silicon wafer is 500 μm (as shown in FIG. 5( a )).
[0077] Further, step (1) includes the following steps:
[0078] (1-1) successively depositing a chromium film and a gold film on the upper end of the silicon substrate 1 by thermal evapo...
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