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Electrostatic discharge protection circuit

An electrostatic discharge protection and electrostatic discharge technology, applied in circuits, electrical components, electrical solid devices, etc., can solve problems such as reducing electrostatic protection, and achieve the effect of eliminating parasitic effects, improving electrostatic protection capabilities, and protecting integrated circuits

Active Publication Date: 2020-06-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the ESD protection circuit has a time delay when discharging, and produces parasitic effects, including parasitic capacitance and / or parasitic inductance, which reduces the ability of electrostatic protection

Method used

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  • Electrostatic discharge protection circuit
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Embodiment Construction

[0026] The ESD protection circuit of the present invention will be described in more detail below in conjunction with the schematic diagram, which shows the preferred embodiment of the present invention. It should be understood that those skilled in the art can modify the present invention described here and still achieve the advantageous effects of the present invention. Therefore, the following description should be understood to be widely known to those skilled in the art, and not as a limitation to the present invention.

[0027] In the following paragraphs, the present invention is described in more detail by way of example with reference to the drawings. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and all use imprecise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of...

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Abstract

The invention discloses an electrostatic discharge protection circuit. The electrostatic discharge protection circuit is connected between a first wafer and a second wafer, wherein the first wafer includes a silicon through hole, and the second wafer comprises an internal chip circuit; and the electrostatic discharge protection circuit includes resistive random access memories, antistatic components and a switch control unit. An electrostatic discharge process can be well realized through the electrostatic discharge protection circuit comprising the switch control unit, the antistatic components and the resistive random access memories, so that an integrated circuit can be protected; and after electrostatic discharge is completed, the resistive random access memories are controlled to be in high-impedance states through the switch control unit, so that the electrostatic discharge protection circuit can be can fully disconnected from the integrated circuit, and therefore, the parasiticeffect of the electrostatic discharge protection circuit can be completely eliminated, and an electrostatic protection capacity can be improved.

Description

Technical field [0001] The invention relates to the field of integrated circuit electrostatic protection circuit design, in particular to an electrostatic discharge protection circuit. Background technique [0002] With the increasing scale of system integration chips, three-dimensional integrated circuits (3DIC) have become a viable alternative circuit for achieving the necessary integration density. In 3DIC, Through Silicon Via (TSV) is widely used to realize vertical interconnection. However, in the 3DIC manufacturing process, when the wafer with TSV in each stacked layer is connected to the metal wire of another wafer, the wafer with TSV is often subjected to a mechanical thinning process. With mechanical friction and other factors , The corresponding static charge will be generated on the wafer with TSV. Then, when the stacked layers are combined, the static charge accumulated in each stacked layer will flow at the same time to generate a large instantaneous current, formin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
Inventor 甘正浩邵芳
Owner SEMICON MFG INT (SHANGHAI) CORP