A method of manufacturing a semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device. The manufacturing method comprises the steps of providing a semiconductor substrate, wherein a plurality of pseudo gates are formed on the semiconductor substrate; performing deposition of a grinding stop layer and an interlayer dielectric layer in sequence to cover the semiconductor substrate and the multiple pseudo gates, wherein the top surface of the interlayer dielectric layer is higher than that of the pseudo gates; performing first chemical-mechanical planarization on the interlayer dielectric layer and stopping atthe grinding stop layer; performing second chemical-mechanical planarization on the interlayer dielectric layer and the grinding stop layer until the grinding stop layer reaches a target thickness; performing etching on the grinding stop layer and stopping at the top surface of the pseudo gates; etching and removing the pseudo gates to form a gate trench; and depositing a metal layer in the gatetrench to form a metal gate. By virtue of the manufacturing method, dish-shaped pits formed on the top surface of the interlayer dielectric layer in a CMP (chemical-mechanical planarization) process can be reduced, thereby reducing metal residues in the dish-shaped pits and improving yield and performance of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the size of semiconductor devices is continuously reduced. High-k metal gates below 32nm have gradually become the mainstream direction of current semiconductor technology development. The chemical-mechanical planarization (CMP) process of the metal gate is one of the most important processes for forming the metal gate. The chemical-mechanical planarization technology has both mechanical polishing and chemical polishing. The wafer surface is planarized to precisely control the metal gate steps. [0003] CMP technology is widely used in the production of metal gate electrodes in high-k metal gates in the 28nm technology node. In the alternative metal gate process, it is often necessary to apply dummy gate polysilicon open chemical ...

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Problems solved by technology

[0004] For the metal gate last process, during the CMP process, due to the relatively high removal rate of the interlayer dielectric layer, the dish-shaped depressions formed on the top surface are relatively large, resulting in the formation of metal gates. In the dish-shaped depressions, because these metal residues can cause short circuits or reduce the reliability of the chip, the performance and yield of the product are reduced

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