Trench-gate superjunction device and manufacturing method thereof

Abstract

The invention discloses a trench-gate superjunction device. A P-type post is divided to an electrode connection P-type post and a floating P-type post which form a first periodic arrangement structurewith a step larger than that of a superjunction unit, a P-type well and a contact hole are formed in the top of the electrode P-type post, the P-type well extends to an N-type post, the contact holeis connected with a source, the P-type well and the contact hole are not formed in the top of the floating P-type post, a length direction of a trench gate and a length direction of the superjunctionstructure are perpendicular to each other and are arranged to form a second periodic arrangement structure, and the step of the second periodic arrangement structure is independently adjusted. The invention also discloses a manufacturing method of the trench-gate superjunction device. By the trench-gate superjunction device, the breakdown voltage and the channel density of the device can be improved, the conduction resistance is reduced, higher Crss can be obtained under very low Vds, the Crss can be slowly reduced within a relatively large Vds range, the speed of the switch process can be reduced, the electromagnetic interference performance of the device in an application circuit can be effectively reduced, and overshoot of a current and a voltage brought by the device in the applicationcircuit can be effectively reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate superjunction (superjunction) device; the invention also relates to a manufacturing method of the trench gate superjunction device. Background technique [0002] The super junction structure is composed of alternately arranged N-type pillars and P-type pillars. If the superjunction structure is used to replace the N-type drift region in the vertical double-diffused MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device, the conduction path is provided through the N-type column in the conduction state, and when the conduction The P-type column does not provide a conduction path; in the off state, the PN column jointly bears the reverse bias voltage, forming a super-junction metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The super-junction MOSFET ca...

AI Technical Summary

Problems solved by technology

The existence of these two factors makes the switching process of the super junction MOSFET prone to excessively low Crss and sharp changes in Crss, resulting in too fast a switching process, resulting in large electromagnetic interference in the application system of the device; even due to the current and voltage Overshoot and cause the circuit to fail

[0019] like image 3 In the structure shown, in the process of the device changing from the on-state to the reverse-off state, in the plateau voltage stage, the Vgs of the device, that is, the gate-source voltage, remains at the plateau voltage, and the Vds, that is, the drain-source voltage of the device, is kept at the plateau voltage when the device is turned on. The Vdson (usually very small) is increased to the power supply voltage Vdd (such as 400 volts) of the circuit. Due to the increase of Vds, the adjacent P-type column 4 and N-type column 3 are laterally depleted, and the N-type column is depleted at a certain voltage. Part or all of the type column 3 is completely depleted, and now the Cgd of the device will become very small, Cgd is Crss, and Cgd is the series connection of Cox and Csi, because dVds / dt=Igp / Cgd (Vds), wherein Vds is the drain The source voltage, the gate current when Igp is the platform voltage, dVds / dt will become very large at this voltage; in this process, the di / dt caused by the nonlinearity of the capacitance is too large, which will also cause the system or device The voltage on the parasitic inductance will overshoot (Ldi / dt), where i is the source leakage current, and L is the parasitic inductance. These factors will cause electromagnetic interference in the circuit or system using the device, affecting the normal operation of the circuit and system ; This situation also exists during the change from the high-voltage reverse cut-off state to the conduction state

This high dVds / dt during the switching process, in addition to causing the oscillation of the application circuit, may also cause excessive current and voltage overshoot of the application system, resulting in circuit damage

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