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Semiconductor structures and methods of forming them

A semiconductor and gate structure technology, applied in the field of semiconductor structures and their formation, to achieve the effects of alleviating short-channel effects, controlling ion distribution, and reducing short-channel effects

Active Publication Date: 2020-06-09
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the performance of fin field effect transistors formed in the prior art needs to be further improved

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] It can be known from the background art that the performance of the semiconductor structure formed in the prior art needs to be improved. The reason is now analyzed in combination with the method for forming the semiconductor structure. refer to Figure 1 to Figure 4 , is a schematic cross-sectional structure diagram corresponding to each step of a method for forming a semiconductor structure.

[0026] The method for forming the semiconductor structure includes: figure 1 As shown, a substrate 10 is provided, and fins 11 located on the substrate 10 are formed. The substrate 10 includes a first region A for forming a first transistor and a second region B for forming a second transistor. , the first transistor is a P-type transistor, and the second transistor is an N-type transistor; an isolation layer 12 is formed on the substrate 10 and between the fins 11, and an oxide layer 13 is formed on the fins 11; A gate structure 14 across the fin, the gate structure 14 cover...

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Abstract

The invention relates to a semiconductor structure and a formation method thereof. The formation method includes the following steps that: a substrate and a plurality of fin portions on the substrateare provided, wherein the substrate includes a first region and a second region, wherein the first region and the second region form two different types of transistors; gate structures which stretch cross the fin portions and cover the partial sidewalls and partial top surfaces of the fin portions are formed; a first stress layer is formed in the fin portion at two sides of the gate structure in the first region; a protective layer is formed; ion implantation is performed on the first stress layer, so that the source / drain doped region of the first transistor is formed; a second stress layer is formed in the fin portion at two sides of the gate structure of the second region; a second protective layer is formed; and ion implantation is performed on the second stress layer, so that the source / drain doped region of the second transistor can be formed. With the semiconductor structure and the formation method thereof of the present invention adopted, excessively high ion energy generatedwhen ion implantation is performed on the first stress layer can be avoided, so that a condition that a semiconductor material is damaged by excessively high energy can be avoided, and the performanceof the semiconductor structure can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase in the density and integration of semiconductor devices, the gate size of planar transistors is also getting smaller and smaller. The ability of traditional planar transistors to control channel currents has become Weak, short channel effect occurs, leakage current increases, and ultimately affects the electrical performance of semiconductor devices. [0003] In order to further reduce the size of MOSFET devices, people have developed multi-side gate field effect transistor structures to improve the controllabil...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L27/092H01L21/336H01L29/78
CPCH01L21/823821H01L27/0924H01L29/66803H01L29/7848
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP