Manufacturing method capable of improving plane VDMOS gate-oxide breakdown

A manufacturing method and planar technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of gate oxide breakdown reduction and achieve simple results

Inactive Publication Date: 2018-06-22
CHONGQING ZHONGKE YUXIN ELECTRONICS
View PDF8 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Based on the characteristics of the planar VDMOS process, although the conventional polysilicon oxidation process or annealing treatment with oxygen atmospher

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Manufacturing method capable of improving plane VDMOS gate-oxide breakdown
  • Manufacturing method capable of improving plane VDMOS gate-oxide breakdown
  • Manufacturing method capable of improving plane VDMOS gate-oxide breakdown

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] A manufacturing method for improving planar VDMOS gate oxide breakdown, characterized in that it includes an epitaxial layer 1, a well region 2, a source region 3, a gate oxide layer 4, a polycrystalline layer 5, a polycrystalline conformal dielectric layer 6, and a dielectric layer 7 and metal layer 8.

[0039] Do the following steps:

[0040] 1) The epitaxial layer 1 is formed using a conventional method.

[0041] 2) Prepare well region 2 and source region 3 .

[0042] The well region 2 is located in the epitaxial layer 1 , and the upper surface of the well region 2 is coplanar with the upper surface of the epitaxial layer 1 . The source region 3 is located in the well region 2 , and the upper surface of the well region 2 is coplanar with the upper surface of the epitaxial layer 1 .

[0043] 3) Depositing the gate oxide layer 4 .

[0044] The gate oxide layer 4 covers the upper surface of the epitaxial layer 1 . The gate oxide layer 4 also covers part of the surf...

Embodiment 2

[0057] A manufacturing method for improving planar VDMOS gate oxide breakdown, characterized in that it includes an epitaxial layer 1, a well region 2, a source region 3, a gate oxide layer 4, a polycrystalline layer 5, a polycrystalline conformal dielectric layer 6, and a dielectric layer 7 and metal layer 8.

[0058] Do the following steps:

[0059] 1) The epitaxial layer 1 is formed using a conventional method.

[0060] 2) Prepare well region 2 and source region 3 .

[0061] The well region 2 is located in the epitaxial layer 1 , and the upper surface of the well region 2 is coplanar with the upper surface of the epitaxial layer 1 . The source region 3 is located in the well region 2 , and the upper surface of the well region 2 is coplanar with the upper surface of the epitaxial layer 1 .

[0062] 3) Depositing the gate oxide layer 4 .

[0063] The gate oxide layer 4 covers the upper surface of the epitaxial layer 1 . The gate oxide layer 4 also covers part of the surf...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to view more

Abstract

The invention discloses a manufacturing method capable of improving plane VDMOS gate-oxide breakdown. The method is characterized in that the method comprises an epitaxial layer, a well region, a source region, a gate oxygen layer, a polycrystalline layer, a polycrystalline shape-preserving dielectric layer, a dielectric layer and a metal layer. The method comprises the following steps: 1) formingthe epitaxial layer through a conventional method; 2) preparing the well region and the source region; 3) carrying out deposition of the gate oxygen layer; 4) carrying out polycrystalline layer deposition and doping; 5) carrying out polycrystalline lithography; 6) forming the polycrystalline shape-preserving dielectric layer through a mode of low-temperature LPCVD of SiO2, wherein the thickness of the polycrystalline shape-preserving dielectric layer is 10nm-60nm; 7) carrying out deposition of the dielectric layer through a conventional method; 8) carrying out hole lithography etching and interconnection metal sputtering; and 9) carrying out interconnection metal lithography and alloy.

Description

technical field [0001] The invention relates to the field of semiconductor power devices, in particular to a manufacturing method for improving planar VDMOS gate oxide breakdown. Background technique [0002] Vertical double-diffusion power MOSFET (VDMOS: Vertical Double-diffusion Metal Oxide Semiconductor) device is widely used in motor speed regulation and inverter due to its advantages of low power consumption, fast switching speed, strong driving capability, and negative temperature coefficient. , electronic switches, automotive electrical appliances and electronic ballasts, etc., are one of the core components of power integrated circuits and power integrated systems. [0003] As the gate oxide process at the core of MOS devices, it plays a vital role in the key parameters and long-term reliability of the device. The deterioration of gate oxide quality will lead to problems such as threshold voltage shift and gate leakage increase. With the reduction of process size, t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66712H01L29/7802
Inventor 肖添唐昭焕王斌吴雪刘勇钟怡杨永晖胡镜影李孝权黄彬
Owner CHONGQING ZHONGKE YUXIN ELECTRONICS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap