Semiconductor structure and formation method thereof

Abstract

The invention relates to a semiconductor structure and a formation method thereof. The method includes the following steps that: a substrate is provided, an interlayer dielectric layer is formed on the substrate, an opening exposing a part of the substrate is formed in the interlayer dielectric layer, a sidewall is formed on the side wall of the opening, and a high-k gate dielectric layer is formed on the surfaces the bottom and sidewall of the opening, and the top of the interlayer dielectric layer; the high-k gate dielectric layer on the top of the interlayer dielectric layer is removed at least; a post-deposition annealing process is performed on the remaining high-k gate dielectric layer; and after the post-deposition annealing process is performed, the opening is filled with a metal layer, so that a metal gate structure can be formed. According to the semiconductor structure and the formation method thereof of the present invention, the high-k gate dielectric layer located at thetop of the interlayer dielectric layer is removed at least, so that the length of the high-k gate dielectric layer can be decreased, and therefore, the expansion amount (or shrinkage amount) of the high-k gate dielectric layer under the influence of the post-deposition annealing process can be decreased, the possibility of the cracking of the high-k gate dielectric layer due to excessive stress can be correspondingly reduced, gate leakage current can be reduced, and the electrical performance and yield of the semiconductor structure formed by using the method can be improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] The main semiconductor device of an integrated circuit, especially a very large scale integrated circuit, is a metal-oxide-semiconductor field effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices continue to decrease, and the geometric dimensions of semiconductor devices follow Moore's law. When the size of semiconductor devices is reduced to a certain extent, various secondary effects brought about by the physical limits of semiconductor devices appear one after another, and it becomes more and more difficult to scale down the feature size of semiconductor devices. Among them, in the field of semiconductor manufacturing, how to solve the problem of large leakage current of semiconductor de...

AI Technical Summary

Problems solved by technology

[0004] Although the introduction of high-k metal gates can improve the electrical performance of semiconductor devices to a certain extent, the electrical performance and yield of semiconductor devices formed by the prior art still need to be improved

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