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Semiconductor device and method of making the same

A manufacturing method and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as difficult to manufacture mobility semiconductor devices

Active Publication Date: 2021-03-09
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The main purpose of this application is to provide a semiconductor device and its manufacturing method to solve the problem that it is difficult to manufacture semiconductor devices with higher quality and higher mobility in the prior art

Method used

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  • Semiconductor device and method of making the same
  • Semiconductor device and method of making the same
  • Semiconductor device and method of making the same

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Embodiment

[0088] The first protective layer 20, the first sacrificial layer 30, the second sacrificial layer 40 and the third sacrificial layer 50 are epitaxially grown on the substrate 10 of single crystal silicon, that is, a figure 1 The sacrificial structure shown, wherein the first protective layer 20 is a silicon dioxide layer with a thickness of 2 nm, the first sacrificial layer 30 is a silicon nitride layer with a thickness of 500 nm, and the second sacrificial layer 40 is a silicon dioxide layer, And the thickness is 20nm, the third sacrificial layer 50 is an amorphous silicon layer, and its thickness is 40nm.

[0089] Photolithography and performing dry anisotropic etching on the sacrificial structure to form a plurality of pre-grooves 61, such as figure 2 shown;

[0090] Remove the third sacrificial layer 50, etch and remove part of the above-mentioned first protective layer 20 and the above-mentioned substrate 10 below the above-mentioned pre-groove 61, so that the surfac...

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Abstract

The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method includes: setting at least one sacrificial structure with a groove on the substrate, the sacrificial structure including a first sacrificial layer and a second sacrificial layer arranged in sequence along a direction away from the substrate; arranging a groove in the groove The second sacrificial layer is removed by etching, so that part of the sidewall of the fin and the surface away from the substrate are exposed; the part of the fin is removed by etching, so that the remaining fins include sequentially along the direction away from the substrate. The sacrificial part and the fin part are provided, and the part of the sacrificial part and the part of the fin part have an interval in the thickness direction of the substrate; an insulating material is arranged on at least the exposed surface of the sacrificial part to form an insulating layer, and the insulating layer is at least full of the sacrificial part and the spacing between the fins. The manufacturing method can produce a semiconductor device with better electrical performance.

Description

technical field [0001] The present application relates to the field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof. Background technique [0002] The advanced CMOS process has entered the node below 14nm. At present, the main mass-produced device is a three-dimensional Fin Field Effect Transistor (3D Fin Field Effect Transisitor, referred to as 3D Fin FET), and its channel material is single crystal silicon. [0003] The process has entered the node below 5nm. In the open literature, Si / GeSi stacked epitaxy is used, and then the sacrificial layer GeSi is removed to leave a silicon channel. [0004] Therefore, the channel material of the public technology is still mainly silicon material. In order to improve channel mobility and improve device performance, it has become an important direction in the industry. How to grow channels with high mobility and better quality such as Ge and GeSi on the substrate Or the channels of t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66795H01L29/785
Inventor 李俊杰李永亮王文武
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI