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Method for manufacturing fine wire (below 30 mum) of packaging substrate by lamination method

A technology for integrated circuits and packaging substrates, applied in the field of integrated circuit manufacturing, can solve the problems of decreased bonding force of dielectric materials, difficulty in meeting the requirements of fine wire production, low energy of copper atoms, etc., and achieves the effect of easy and controllable operation.

Inactive Publication Date: 2018-11-20
陈长生
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the wiring density of the packaging substrate increases, the width of the wire becomes thinner and thinner, and its bonding force with the dielectric material decreases, which is more likely to cause the wire to shift or fall off, which seriously affects the process feasibility and product reliability.
[0003] The bonding force between wires and dielectric materials has become one of the key issues to be solved in the production of fine wires on high-density packaging substrates. According to previous relevant literature reports, in order to improve the bonding force between wires and dielectric materials, there are mainly the following two methods: 1. The first is to use baking treatment before and after electroless copper plating in order to remove the residual water vapor in the resin and prevent the residual water vapor from causing the chemical copper plating layer to bubble and fall off. At the same time, baking can eliminate the internal stress and lattice rearrangement of the electroless copper plating layer. In order to increase the binding force between electroless copper plating and dielectric material, but it does not change the bonding interface structure between wire and dielectric material, the improvement of the bonding force between electroless copper plating and dielectric material is limited, and it cannot meet the requirements of finer and finer wire production; the second One uses copper ion sputtering instead of electroless copper plating, in order to improve the bonding force by changing the bonding interface structure between the wire and the dielectric material, but because the sputtering uses argon ions to hit the metal target, the target is sputtered, and the sputtered copper Atoms are deposited on the surface of the ABF film. Because the atomic weight of argon is smaller than that of the target copper, the sputtered copper atoms have low energy and can only adhere to the surface of the dielectric material, resulting in a low bonding force between the wire and the dielectric material, which is difficult to meet the requirements of fine wire production.

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  • Method for manufacturing fine wire (below 30 mum) of packaging substrate by lamination method
  • Method for manufacturing fine wire (below 30 mum) of packaging substrate by lamination method
  • Method for manufacturing fine wire (below 30 mum) of packaging substrate by lamination method

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Embodiment Construction

[0029] Below in conjunction with accompanying drawing and embodiment this patent is further explained and illustrated. But the scope of protection of this patent is not limited to the specific implementation.

[0030] Implementation example

[0031] In this example, fine wires with a line width / line spacing of 20 μm / 20 μm are produced on the high-density packaging substrate interlayer dielectric material ABF film produced by the build-up process. The specific production process is as follows:

[0032] Lamination technology is used to complete the interlayer dielectric material ABF film pressing and curing the package substrate to be processed → ABF film surface mechanical grinding → baking plate → ion implantation of nickel → electroless copper plating → baking → micro-etching chemical treatment → paste photosensitive dry film → Pattern transfer → pattern electroplating copper → photosensitive dry film removal → differential etching → complete fine wire production. Specific ...

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Abstract

A method for manufacturing fine wires (below 30 mum) of a packaging substrate by a lamination method includes such steps as ion implanting nano-depth nickel atom doped layer on the surface of dielectric material ceramic powder reinforced modified epoxy resin film (ABF film), electroless copper plating is performed to form a copper layer of 3-5mum, and the electroless copper plating is then suffered by baking and hydrogen peroxide sulfate micro-etching chemical treatment of the electroless copper plating layer, and then electroplating is performed to thicken the pattern conductor to the required thickness of 15-20 mum through a photosensitive dry film, exposure, development and pattern electroplating process. Then the photosensitive dry film is removed, and differential etching is obtainedby adopting Hydrogen peroxide sulfate etching solution to obtain the required fine wire. The method improves the bonding force between the fine wire and the dielectric substrate, avoids the fine wirefrom shifting or falling off in the subsequent processing process, is simple and controllable in operation, and meets the manufacturing requirements of the high-density packaging substrate for integrated circuits.

Description

technical field [0001] The invention relates to a method for manufacturing fine wires of a high-density packaging substrate for an integrated circuit produced by a lamination method, and belongs to the field of integrated circuit manufacturing. Background technique [0002] With the improvement of integrated circuit manufacturing capabilities, the difficulty of manufacturing organic packaging substrates for integrated circuits has gradually increased. At present, the mainstream interconnection method between chips and packaging substrates is the flip chip (FC) method, and the manufacturing process of organic packaging substrates is also increasing. From the traditional printed board manufacturing process to the high-density interconnection build-up (build-up) process. The lamination structure of the high-density packaging substrate for integrated circuits produced by the lamination method is n+2+n, which is composed of two sides of the middle core board plus n-layer intercon...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/76826
Inventor 陈长生
Owner 陈长生