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Design method of high-power vertical tiled multi-channel digital transceiver sub-array

A design method and high-power technology, which is applied to the design of two-dimensional active digital phased array radar transceiver components or transceiver sub-arrays, in the field of radar, to achieve excellent platform adaptability, easy disassembly and maintenance, and save carrier space.

Active Publication Date: 2022-07-22
CNGC INST NO 206 OF CHINA ARMS IND GRP
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Problems solved by technology

The present invention adopts the digital-analog mixed transceiver SOC to effectively reduce the size, power consumption and cost of the active circuit; adopts the vertical and cableless interconnection between filter layers to solve the problem of vertical transmission of high-power microwave signals, which can ensure efficient transmission of microwave signals, It can also reduce the volume of tiles and realize the circuit layout within the area of ​​a single radiation unit; the heat dissipation problem of high-power heating elements is solved by adopting the form of heat sink on the back of the power amplifier

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  • Design method of high-power vertical tiled multi-channel digital transceiver sub-array
  • Design method of high-power vertical tiled multi-channel digital transceiver sub-array
  • Design method of high-power vertical tiled multi-channel digital transceiver sub-array

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Embodiment Construction

[0022] The present invention will now be further described in conjunction with the embodiments and accompanying drawings:

[0023] The principle block diagram of the high-power vertical tiled multi-channel digital transceiver sub-array according to the present invention is as follows: image 3 As shown, the uplink baseband signal is phase-controlled by the FPGA, together with the system clock signal and the local oscillator signal LO through the SOC to generate the emission excitation signal, which is sent to the antenna radiation unit through the power amplifier, circulator and RF filter; the target received by the antenna is reflected back The wave signal is sent to the SOC with low noise through the radio frequency filter, circulator and limiter, and is processed by down-conversion with the local oscillator signal LO inside the SOC to generate a digital received signal.

[0024] The vertical tile-type integration method of the present invention requires that the transceiver...

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Abstract

The invention relates to a high-power vertical tile type multi-channel digital transceiver sub-array design method. The digital-analog hybrid transceiver SOC is used to effectively reduce the size, power consumption and cost of the active circuit; the vertical and cableless interconnection between filter layers is adopted. To solve the problem of vertical transmission of high-power microwave signals, it can not only ensure the efficient transmission of microwave signals, but also reduce the size of the tile, and realize the circuit layout within the area of ​​a single radiation unit; the high-power heating element is solved by using the power amplifier back-mounted radiator. cooling problem.

Description

technical field [0001] The invention relates to the technical field of radar, in particular to a high-power vertical tile type multi-channel digital transceiver sub-array design method, which can be applied to the design field of two-dimensional active digital phased array radar transceiver components or transceiver sub-arrays. Background technique [0002] The key component in the two-dimensional active phased array radar is the transceiver component, and the number of front component units is huge. Most of them are integrated in the form of transceiver sub-arrays. Its function is to realize the generation, phase shift and power amplification of the radar excitation signal; the low-noise amplification and down-conversion of the target reflected echo signal, and the digital signal sampled by AD is transmitted to the signal processor after photoelectric conversion. [0003] At present, there are two main ways to integrate active phased array radar transceiver fronts: paralle...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01S13/00G01S7/285G01S7/282G01S7/35
CPCG01S7/282G01S7/285G01S7/352G01S13/00G01S2013/0254
Inventor 雷国忠崔敏
Owner CNGC INST NO 206 OF CHINA ARMS IND GRP
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