A silicon carbide metal oxide semiconductor field effect transistor and its manufacturing method
An oxide semiconductor and field effect transistor technology, which is applied in the field of semiconductor and power semiconductor devices and their preparation, can solve the problems of high gate oxide electric field blocking state, breakdown, and increase of JFET width, etc. Conductivity, effect of suppressing electric field strength
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0052] Embodiment 1: a silicon carbide metal oxide semiconductor field effect transistor according to the present invention, comprising an epitaxial layer 4 and a drain 2 located on the back of the epitaxial layer 4; as figure 1 As shown, the epitaxial layer 4 is composed of an N-type lightly doped drift layer 41 and an N-type heavily doped substrate 42. The thickness and doping concentration of the N-type lightly doped drift layer 41 can be selected according to the blocking voltage of the device.
[0053] The P well 5 is adjacent to the N-type lightly doped drift layer 41 and distributed on both sides of the N-type lightly doped drift layer 41, and the width between the P wells 5 is the width of the JFET region;
[0054] The first conductivity type region 1 is located in the JFET region, the doping concentration of the first conductivity type region 1 is higher than that of the N-type lightly doped drift layer 41, the bottom is higher than the bottom of the JFET region, and t...
Embodiment 2
[0068] Embodiment 2: Another structure of the silicon carbide metal oxide semiconductor field effect transistor according to the present invention is as follows image 3 As shown, the difference from the structure of Example 1 is that three first conductivity type regions 1 at the same height are formed in the JFET region by ion implantation, and the width of each first conductivity type 1 is different. The first conductivity type region The doping concentration of 1 is higher than that of the N-type lightly doped drift layer 41, the bottom is higher than the bottom of the JFET region, and the tops of the three first conductivity type regions 1 extend to the lower surface of the gate oxide layer 8, that is, the surface of the device.
[0069] Such as Figure 4 As shown in the figure a-i, the preparation method of the structure of Example 2 of the present invention is:
[0070] (1) if Figure 4 middle a map and Figure 4 As shown in Figure b, an N-type lightly doped drift la...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


