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A silicon carbide metal oxide semiconductor field effect transistor and its manufacturing method

An oxide semiconductor and field effect transistor technology, which is applied in the field of semiconductor and power semiconductor devices and their preparation, can solve the problems of high gate oxide electric field blocking state, breakdown, and increase of JFET width, etc. Conductivity, effect of suppressing electric field strength

Active Publication Date: 2021-03-02
NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Purpose of the invention: In order to solve the above problems, the present invention proposes a silicon carbide metal oxide semiconductor field effect transistor structure, which solves the problem that the increase in the width of the JFET causes the electric field of the device gate oxide to be too high when it is in the blocking state, and the problem of breakdown occurs

Method used

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  • A silicon carbide metal oxide semiconductor field effect transistor and its manufacturing method
  • A silicon carbide metal oxide semiconductor field effect transistor and its manufacturing method
  • A silicon carbide metal oxide semiconductor field effect transistor and its manufacturing method

Examples

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Embodiment 1

[0052] Embodiment 1: a silicon carbide metal oxide semiconductor field effect transistor according to the present invention, comprising an epitaxial layer 4 and a drain 2 located on the back of the epitaxial layer 4; as figure 1 As shown, the epitaxial layer 4 is composed of an N-type lightly doped drift layer 41 and an N-type heavily doped substrate 42. The thickness and doping concentration of the N-type lightly doped drift layer 41 can be selected according to the blocking voltage of the device.

[0053] The P well 5 is adjacent to the N-type lightly doped drift layer 41 and distributed on both sides of the N-type lightly doped drift layer 41, and the width between the P wells 5 is the width of the JFET region;

[0054] The first conductivity type region 1 is located in the JFET region, the doping concentration of the first conductivity type region 1 is higher than that of the N-type lightly doped drift layer 41, the bottom is higher than the bottom of the JFET region, and t...

Embodiment 2

[0068] Embodiment 2: Another structure of the silicon carbide metal oxide semiconductor field effect transistor according to the present invention is as follows image 3 As shown, the difference from the structure of Example 1 is that three first conductivity type regions 1 at the same height are formed in the JFET region by ion implantation, and the width of each first conductivity type 1 is different. The first conductivity type region The doping concentration of 1 is higher than that of the N-type lightly doped drift layer 41, the bottom is higher than the bottom of the JFET region, and the tops of the three first conductivity type regions 1 extend to the lower surface of the gate oxide layer 8, that is, the surface of the device.

[0069] Such as Figure 4 As shown in the figure a-i, the preparation method of the structure of Example 2 of the present invention is:

[0070] (1) if Figure 4 middle a map and Figure 4 As shown in Figure b, an N-type lightly doped drift la...

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Abstract

The invention discloses a silicon carbide metal oxide semiconductor field effect transistor and a preparation method thereof. The structure of the silicon carbide metal oxide semiconductor field effect crystal includes an epitaxial layer, a drain electrode, a first conductivity type well region, and a second conductivity type well region. The source region, the heavily doped region of the first conductivity type, the source electrode, the gate oxide layer, the gate electrode, the passivation protection layer and several regions of the first conductivity type. The present invention introduces the region of the first conductivity type, which can increase the width of the JFET while suppressing the electric field strength in the gate oxide of the device, thereby increasing the width of the JFET region, reducing the resistance of the JFET region, and improving device conduction characteristics.

Description

technical field [0001] The invention relates to a semiconductor and power semiconductor device and a manufacturing method thereof, in particular to a silicon carbide MOSFET device and a manufacturing method thereof. Background technique [0002] At present, silicon carbide MOSFET devices have serious gate oxide reliability problems. In order to improve the reliability of the device, the electric field strength in the gate oxide of SiC MOSFET devices must be reduced. [0003] In order to improve the forward conduction characteristics of silicon carbide MOSFET devices, it is generally desired to increase the width of the JFET region and reduce the resistance of the JFET region. However, the increase in the width of the JFET will weaken the ability of the adjacent P well to suppress the electric field of the gate oxide, which will cause reliability problems in the gate oxide. Contents of the invention [0004] Purpose of the invention: In order to solve the above problems, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/0607H01L29/66712H01L29/7802H01L21/046H01L29/0619H01L29/0623H01L29/1608H01L29/66068
Inventor 杨同同柏松
Owner NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD