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Parallel test structure

A technology for testing modules and testing voltage, which is applied in the direction of measuring electricity, semiconductor/solid-state device testing/measurement, and measuring devices, and can solve problems such as not being cost-effective

Active Publication Date: 2019-03-05
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

There is no cost-effective test implementation (architecture and test system) for massively parallel TDDB testing at the level of a single chip

Method used

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Embodiment Construction

[0014] Manufacturers often perform tests to help determine dielectric failure expectations and thus determine circuit reliability. Generally, the primary test performed to determine dielectric failure expectations is the TDDB test.

[0015] TDDB testing involves determining when a portion of a circuit, such as the gate of a transistor, breaks down. This can be caused by a weak part of the dielectric. It may be determined when a dielectric portion of a circuit portion breaks down at certain specific current levels, voltage levels, and / or temperature levels. In the case of a transistor, breakdown would prevent the transistor's gate from operating properly as a switch that controls the flow of current through the transistor's source and drain.

[0016] TDDB testing is typically performed by using a basic test structure (typically a two-terminal capacitor) at a temperature of about 125°C under a DC bias condition of 1.5 to 20V. The leakage current is recorded for each device fo...

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Abstract

The invention relates to a parallel test structure. An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test.The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt aroundthe decoder upon failure of the device under test.

Description

technical field [0001] The present disclosure relates to the design of integrated circuits, and more particularly to structures and methods for testing a large number of devices in parallel. Background technique [0002] An integrated circuit (IC) is a semiconductor device that includes many small interconnected components such as diodes, transistors, resistors, and capacitors. These components work together to enable the integrated circuit to perform tasks, such as controlling electronic devices, or performing logic operations. Integrated circuits are found in computers, calculators, cell phones, and many other electronic devices. [0003] Integrated circuits and other semiconductor devices are fabricated on small squares (also called "chips") that are filled with multiple layers of components such as transistors, resistors, and capacitors during the process. In general, a variety of process technologies are currently implemented, wherein, for many types of complex circui...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66
CPCH01L22/14H01L22/30G01R31/129G01R31/2858G01R31/2879H01L22/34H01L21/67253G01R3/00G01R31/1272
Inventor 沈添A·库马尔宋云成K·B·耶普R·G·小菲利皮曹琳珺S·乔伊C·J·克里斯琴森P·R·朱斯蒂孙
Owner GLOBALFOUNDRIES U S INC MALTA
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