32-bit MCU chip test system and test method thereof

Abstract

The invention discloses a 32-bit MCU chip test system and a test method thereof. The test system comprises an ATE test machine table and an embedded microprocessor, and the ATE test machine table is connected with the embedded microprocessor through a data transmission interface; a control module used for fulfilling core calculation and control functions, a storage module, a firmware updating module, a multi-power-supply management module, a self-adaptive interface module, a contact detection module, a scanning module, an index testing module and a yield control module are arranged in the embedded microprocessor. According to the invention, multi-platform cooperative processing is used; the chip simulation performance characteristics are tested and subjected to yield analysis, multiple simulation parameters can be tested at the same time, the multi-power-supply control and high-precision line scanning technology is adopted, manual participation is not needed in the whole testing and yield analysis control process, yield information of multiple batches of products can be automatically completed and analyzed, and convenience and high efficiency are achieved.

Description

technical field [0001] The invention belongs to the field of chip testing, and in particular relates to a testing method for the performance of 32-bit MCU chip products and a product yield control method in the chip production process. Background technique [0002] Most of the current 32-bit MCU chip analog semaphore tests are tested in the R&D stage. After the test is completed, there is no effective monitoring of the performance of the main modules in the mass production CP stage. At the same time, the chip will affect the quality of the product due to factors such as design, process, and packaging. As a result, the client will encounter application problems and low batch yields due to batch process deviations, which will undoubtedly increase the company's customer complaints and seriously affect brand competitiveness. The current test equipment cannot analyze and control the yield rate of the chips tested in batches, which greatly limits the improvement of the chip design...

AI Technical Summary

Problems solved by technology

The application discloses testing through the upper computer and the lower computer, but does not reveal the communication protocol and specific serial port configuration instructions

[0004] For 32-bit MCU chip products, the existing CP testing machine cannot provide an analog signal supply below 1mV. The effective accuracy of testing multiple analog indicators is low, the flexibility is poor, and the repeated test time is long, and the yield rate of the chip cannot be determined. The analysis and control of the situation will bring difficulties to the subsequent yield analysis work, and there is no contact resistance and leakage current detection, voltage and current signal quantity test, ADC test and power supply voltage generation, etc. are all independent and cannot be carried out simultaneously. For the simulation performance test, the test platform for different projects needs to be redeveloped. Due to the accuracy problem, the ADC cannot be effectively evaluated, and the repetitive workload is heavy. There is no complete detection method to solve the problem of the chip due to the high-precision benchmark. A lot of repetitive work increases the cost of manpower, material and time resources, and a lot of internal friction leads to high testing costs

[0005] Affected by traditional development ideas, the CP test development mode is not implemented in the form of functional modules composed of external devices, and lacks a highly integrated coordinated test system, which restricts the efficiency of mass production CP tests and does not meet the company's business development needs

Images