Transistor and manufacturing method thereof
A transistor and gate technology, applied in the field of transistors and their fabrication, can solve the problems of difficulty in mass production of AlGaN/GaN HEMT devices, weakening the advantages of GaN materials, and increasing device fabrication costs, so as to prevent premature degradation of the gate dielectric and prolong its use. The effect of longevity and operability
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Embodiment 1
[0050] Such as figure 1 Shown is the fabrication method of the highly reliable GaN MOS-HEMT device (or the AlGaN GaN HFET device of MOS structure) with strong short-circuit capability of the present embodiment, including the following process:
[0051] St1, preparing GaN epitaxial wafers, depositing GaN extension layers and p-GaN layers;
[0052] Such as figure 2 As shown, the prepared GaN epitaxial wafer includes a Si substrate 11 (Si substrate), a GaN buffer layer 12 (High resistive buffer layer), a GaN channel layer 13 (GaN channel) and an AlGaN barrier layer 14 deposited in sequence, each The layers are all grown by MOCVD method, such as metal organic Ga(CH 3 ) 3 and ammonia (NH 3 ) react at a high temperature greater than 1050°C to generate GaN deposited on the Si substrate. Adjustments to the composition of the reactants can result in slightly different compositions for each layer.
[0053]Among them, the crystal structure of GaN and AlGaN is a wurtzite structure,...
Embodiment 2
[0081] The highly reliable GaN MOS-HEMT device (or the AlGaNGaN HFET device of MOS structure) with strong short-circuit capability of the present embodiment is as follows: Figure 19 As shown, it can be produced through the St7 process of Embodiment 1, which includes a GaN epitaxial wafer, isolating and distributing the source, gate, junction gate and drain on the upper surface of the GaN epitaxial wafer, and forming the source, gate, The intermediate layer between the junction gate and the drain.
[0082] Among them, the GaN epitaxial wafer includes a Si substrate 11, a GaN buffer layer 12, a GaN channel layer 13, and an AlGaN barrier layer 14 deposited in sequence, and a two-dimensional electron gas is formed between the AlGaN barrier layer 14 and the GaN channel layer 13. (2-DEG).
[0083] The source includes a source metal electrode region 31, the gate includes a gate window 43 of a "V"-shaped groove, and sequentially deposited gate dielectric 42 and gate metal electrode ...
Embodiment 3
[0089] Such as Figure 23Shown is the GaN MOS-HEMT device of this embodiment, which can be produced through the St8 process of the first embodiment. A TOES layer 62, SiN protection layer 63 and second TOES layer 64 are formed between the source, gate, junction gate and drain.
[0090] The upper surfaces of the source, gate and drain are exposed outside the SiN protective layer 63 through the VIA contact holes of the second TOES layer 64, that is, the bottom surfaces of the three VIA contact holes of the second TOES layer 64 are the source, gate and the upper surface of the drain, so that the source metal electrode region, the gate metal electrode region and the drain metal electrode region can be connected to external devices; the upper surface of the junction gate is covered by a SiN protective layer 63 .
[0091] The design of this embodiment enables the GaN MOS-HEMT device to obtain better protection, a more complete structure, and a longer service life.
[0092] After th...
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Abstract
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Application Information
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