Preparation method of high temperature resistant QFN package structure

Abstract

The invention discloses a preparation method of a high temperature resistant QFN package structure. The QFN package structure comprises a heat dissipation pad, a chip and conductive pads which are located in an epoxy insulator, wherein the chip is located on the heat dissipation pad, a plurality of conductive pads are disposed around the heat dissipation pad, and the conductive pads and the chip are connected by a lead. The method comprises the following steps of S1, firstly uniformly mixing the silicon micropowder and the flame retardant with gamma-methacryloxypropyltrimethoxysilane for surface treatment; S2, adding epoxy resin, novolac resin, liquid nitrile rubber, diphenylmethane diisocyanate, diethyl pyrocarbonate, dibenzyl phosphate, 5-fluoro-2-methoxyaniline, 2,4,6-tris(dimethylaminomethyl)phenol and a release agent. The preparation method has excellent heat resistance under the premise of ensuring good mechanical properties, and the glass transition temperature reaches 190-230 DEG C, which can meet the requirements of the packaging of high power and high heating chips.

Description

technical field [0001] The invention belongs to the technical field of leadless packaging, and in particular relates to a method for preparing a high temperature resistant QFN packaging structure. Background technique [0002] QFN packaging is widely used in PCB boards, and the application of QFN packaging has greatly promoted the development of electronic technology. The QFN package has excellent thermal performance, mainly because there is a large area of ​​heat dissipation soldering at the bottom of the package. In order to effectively conduct heat from the chip to the PCB, the bottom of the PCB must be designed with corresponding heat dissipation pads and heat dissipation vias. The pad provides a reliable soldering area, and the thermal via provides a heat dissipation path. [0003] The conventional QFN package design in the PCB usually has a large-area heat dissipation pad, which is usually grounded. Although this heat dissipation pad can play the role of chip heat dis...

AI Technical Summary

Problems solved by technology

[0003] The conventional QFN package design in the PCB usually has a large-area heat dissipation pad, which is usually grounded. Although this heat dissipation pad can play the role of chip heat dissipation, it is often too large to Too much tin brushing during the (SMT) process will cause a short circuit between the large heat dissipation pad in the center of the QFN package and other small conductive pads

In addition, with the continuous development of integrated circuit packaging towards high density, high integration, and high speed, the packaging structure is also facing a series of reliability risks caused by chip heating.

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