Preparation method of high temperature resistant QFN package structure

A technology of packaging structure and high temperature resistance, which is used in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as excessive pads and short circuits, reduce usage, improve cross-linking density, and improve mechanical properties. performance effect

Active Publication Date: 2019-06-18
西安航思半导体有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The conventional QFN package design in the PCB usually has a large-area heat dissipation pad, which is usually grounded. Although this heat dissipation pad can play the role of chip heat dissipation, it is often too large to Too much tin brushing during the (SMT) process will cause a short circuit between th

Method used

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  • Preparation method of high temperature resistant QFN package structure
  • Preparation method of high temperature resistant QFN package structure
  • Preparation method of high temperature resistant QFN package structure

Examples

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Embodiment 1~4

[0028] Embodiments 1 to 4: A preparation method of a high temperature resistant QFN packaging structure, the high temperature resistant QFN packaging structure includes a heat dissipation pad 1, a chip 3 and a conductive pad 4 located in an epoxy insulator 6, and the chip 3 is located in On the heat dissipation pad 1, and the silver paste layer 2 is arranged between the chip 3 and the heat dissipation pad 1, and several conductive pads 4 are arranged on the periphery of the heat dissipation pad 1, and the conductive pad 4 and the chip 3 pass through A lead wire 5 is connected;

[0029] The side of the heat dissipation pad 1 away from the chip 3 is provided with a separation groove 11, the width of the separation groove 11 is 0.1-0.3 mm, and the separation groove 11 divides the side of the heat dissipation pad 1 away from the chip 3 into equal parts. At least two single pads 13, the separation grooves 11 are filled with heat-conducting insulating strips 12, the walls of the sep...

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Abstract

The invention discloses a preparation method of a high temperature resistant QFN package structure. The QFN package structure comprises a heat dissipation pad, a chip and conductive pads which are located in an epoxy insulator, wherein the chip is located on the heat dissipation pad, a plurality of conductive pads are disposed around the heat dissipation pad, and the conductive pads and the chip are connected by a lead. The method comprises the following steps of S1, firstly uniformly mixing the silicon micropowder and the flame retardant with gamma-methacryloxypropyltrimethoxysilane for surface treatment; S2, adding epoxy resin, novolac resin, liquid nitrile rubber, diphenylmethane diisocyanate, diethyl pyrocarbonate, dibenzyl phosphate, 5-fluoro-2-methoxyaniline, 2,4,6-tris(dimethylaminomethyl)phenol and a release agent. The preparation method has excellent heat resistance under the premise of ensuring good mechanical properties, and the glass transition temperature reaches 190-230 DEG C, which can meet the requirements of the packaging of high power and high heating chips.

Description

technical field [0001] The invention belongs to the technical field of leadless packaging, and in particular relates to a method for preparing a high temperature resistant QFN packaging structure. Background technique [0002] QFN packaging is widely used in PCB boards, and the application of QFN packaging has greatly promoted the development of electronic technology. The QFN package has excellent thermal performance, mainly because there is a large area of ​​heat dissipation soldering at the bottom of the package. In order to effectively conduct heat from the chip to the PCB, the bottom of the PCB must be designed with corresponding heat dissipation pads and heat dissipation vias. The pad provides a reliable soldering area, and the thermal via provides a heat dissipation path. [0003] The conventional QFN package design in the PCB usually has a large-area heat dissipation pad, which is usually grounded. Although this heat dissipation pad can play the role of chip heat dis...

Claims

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Application Information

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IPC IPC(8): H01L23/29H01L23/367H01L21/56
CPCH01L2224/32245H01L2224/48091H01L2224/48247H01L2224/73265H01L2924/181H01L2924/00012H01L2924/00014H01L2924/00
Inventor 马磊党鹏杨光彭小虎王新刚庞朋涛任斌王妙妙
Owner 西安航思半导体有限公司
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