Reverse terminal structure of bidirectional withstand voltage power device based on step etching in drift region
A technology of power devices and terminal structures, which is applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as difficult to apply SiC material process, increase conduction power consumption of series diodes, influence of package parasitic parameters, etc., to avoid avalanche strikes The effect of wear, reduction of electric field, and reduction of charge flux
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Embodiment 1
[0022] The reverse terminal structure of the bidirectional withstand voltage power device based on step etching in the drift region designed in this embodiment, such as figure 1 As shown, it includes a P-type semiconductor drift region 1 and an N-type semiconductor region 2 below it. The N-type semiconductor region 2 is a substrate layer and has a stepped structure at the edge of the drift region 1 with four steps.
[0023] In this embodiment, the ratio of the depth to the width of each step is a fixed value. The sum of the depths of each step is greater than the thickness of the P-type semiconductor drift region 1 , that is, the lowest step is formed jointly by the N-type semiconductor region 2 and the P-type semiconductor drift region 1 . In this example, the semiconductor materials of the P-type semiconductor drift region 1 and the N-type substrate 2 are SiC materials, and may also be silicon or other semiconductor materials.
[0024] The working principle of this embodime...
Embodiment 2
[0027] Such as figure 2 As shown, compared with Embodiment 1, the N-type semiconductor region 2 of this embodiment includes upper and lower layers, wherein the lower layer is the substrate layer 2b, the upper layer is adjacent to the semiconductor drift region 1 of the first conductivity type, and the upper layer is the buffer layer 2a , the doping concentration of the substrate layer 2b is higher than that of the buffer layer 2a. Wherein, the lowest step in the stepped structure is jointly formed by the buffer layer 2 a of the N-type semiconductor region 2 and the P-type semiconductor drift region 1 .
Embodiment 3
[0029] Such as image 3 As shown, compared with the embodiment 2, the step structure at the edge of the semiconductor drift region 1 of the present embodiment has a changed step aspect ratio. The width of the step near the bottom is larger than that of the top step, which is more conducive to transferring the high electric field region to the body, thereby further reducing the terminal electric field of the edge step.
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